W9751G6KB-25 datasheet(19/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

Download	87 Pages

Scroll/Zoom	100%

Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

Logo

19 / 87 page

W9751G6KB

Publication Release Date: Sep. 03, 2012

- 19 -

Revision A04

CMD

CLK

ODT

Rtt

Updating

New setting

tIS

tMOD,min

tMOD,max

tAOFD

EMRS

NOP

Old setting

1) EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).

2) "setting" in this diagram is the Register and I/O setting, not what is measured from outside.

Figure 10

– ODT update delay timing - tMOD

However, to prevent any impedance glitch on the channel, the following conditions must be met.



tAOFD must be met before issuing the EMRS command.



ODT must remain LOW for the entire duration of tMOD window, until tMOD,max is met.

Now the ODT is ready for normal operation with the new setting, and the ODT signal may be raised

again to turned on the ODT. Following timing diagram shows the proper Rtt update procedure.

CLK

CMD

ODT

Rtt

Old setting

New setting

tAOND

tIS

tMOD,max

tAOFD

EMRS

NOP

1) EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).

2) "setting" in this diagram is what is measured from outside.

Figure 11

– ODT update delay timing - tMOD, as measured from outside

Similar Part No. - W9751G6KB-25

Manufacturer	Part #	Datasheet	Description
Winbond	W9751G6KB	1Mb / 87P	8M ??4 BANKS ??16 BIT DDR2 SDRAM
Microchip Technology	W9751G6KB25I	1Mb / 56P	SAMA5D2 System in Package (SIP) MPU with up to 1 Gbit DDR2 SDRAM or 2 Gbit LPDDR2 SDRAM 2021

More results

Similar Description - W9751G6KB-25

Manufacturer	Part #	Datasheet	Description
Elite Semiconductor Mem...	M13S128324A-2M	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S5121632A-2S	705Kb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S2561616A-2S	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9412G2IB4	832Kb / 50P	Double Data Rate architecture; two data transfers per clock cycle
Winbond	W9412G6JH-5	1Mb / 53P	Double Data Rate architecture; two data transfers per clock cycle
Elite Semiconductor Mem...	M13S2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Elite Semiconductor Mem...	M13L32321A-2G	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W631GG6KB-15	3Mb / 158P	Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Mem...	M13L2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W972GG6JB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle

More results

W9751G6KB-25 Datasheet(PDF) 19 Page - Winbond

W9751G6KB-25 Datasheet(HTML) 19 Page - Winbond

Similar Part No. - W9751G6KB-25

Similar Description - W9751G6KB-25

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

Datasheet Download

Link URL