W9751G6KB-25 datasheet(13/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 13 -

Revision A04

8.2.2.3

Extend Mode Register Set Command (2), EMR (2)

( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "H", A0 to A12 = Register data)

The extended mode register (2) controls refresh related features. The default value of the extended

mode register (2) is not defined, therefore the extended mode register (2) must be programmed during

initialization for proper operation.

The DDR2 SDRAM should be in all bank precharge state with CKE already high prior to writing into

the extended mode register (2). The mode register set command cycle time (tMRD) must be satisfied to

complete the write operation to the extended mode register (2). Mode register contents can be

changed using the same command and clock cycle requirements during normal operation as long as

all banks are in the precharge state.

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

0

SELF

0*

1

Address Field

Extended Mode Register (2)

0*

1

A7

1

0

Disable

High Temperature Self Refresh Rate Enable

Enable*

2

BA0

1

BA1

BA0

MRS mode

0

1

MRS

EMR (1)

EMR (2)

EMR (3)

BA1

Notes:

1. The rest bits in EMR (2) is reserved for future use and all bits in EMR (2) except A7, BA0 and BA1 must be programmed to 0

when setting the extended mode register (2) during initialization.

2. When DRAM is operated at 85°C < TCASE

≤ 95°C or 105°C the extended Self Refresh rate must be enabled by setting bit

A7 to

“1” before the Self Refresh mode can be entered.

Figure 4

– EMR (2)

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