W9751G6KB-25 datasheet(11/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 11 -

Revision A04

SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2

does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must

be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the

table for specific codes.

BA0

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

PD

WR

DLL

BT

CAS Latency

Burst Length

TM

A8

0

1

DLL Reset

No

Yes

BA1

BA0

0

1

0

1

MRS mode

MR

EMR (1)

EMR (2)

EMR (3)

A12

1

0

Active power down exit time

Fast exit (use tXARD)

Slow exit (use tXARDS)

Burst Length

Address Field

Mode Register

Write recovery for Auto-precharge

CAS Latency

A6

0

1

A5

0

1

0

1

A4

0

1

0

1

0

1

0

Latency

Reserved

3

4

5

7

6

Reserved

A2

0

A1

1

A0

0

1

BL

4

8

A11

0

1

A10

0

1

0

1

A9

0

1

0

1

0

1

0

WR *

Reserved

2

3

4

5

6

8

7

A7

0

1

Mode

Normal

Test

A3

0

1

Burst Type

Sequential

Interleave

0

BA1

0

Note:

1. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min.

WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this

value. This is also used with tRP to determine tDAL.

Figure 2

– Mode Register Set (MRS)

8.2.2

Extend Mode Register Set Commands (EMRS)

8.2.2.1

Extend Mode Register Set Command (1), EMR (1)

( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L", A0 to A12 = Register data)

The extended mode register (1) stores the data for enabling or disabling the DLL, output driver

strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended

mode register (1) is not defined, therefore the extended mode register (1) must be programmed during

initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE

already high prior to writing into the extended mode register (1). The mode register set command

cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1).

Extended mode register (1) contents can be changed using the same command and clock cycle

requirements during normal operation as long as all banks are in the precharge state. A0 is used for

DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the

additive latency, A[9:7] are used for OCD control, A10 is used for DQS disable. A2 and A6 are used

for ODT setting.

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