W9751G6KB-25 datasheet(10/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 10 -

Revision A04

Notes:

1. To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.

2. VREF must be within

 300 mV with respect to VDDQ/2 during supply ramp time.

3. VDD/VDDL voltage ramp time must be no greater than 200 mS from when VDD ramps from 300 mV to VDD min.

4. The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be no

greater than 500 mS

tCH tCL

tIS

400nS

NOP

PRE

ALL

EMRS

MRS

PRE

ALL

REF

MRS

REF

EMRS

ANY

CMD

tRP

tMRD

tRP

tRFC

tOIT

Follow OCD

Flow chart

OCD

CAL. Mode

Exit

OCD

Default

min 200 Cycle

DLL

Reset

DLL

Enable

CLK

CKE

Command

ODT

tMRD

Figure 1

– Initialization sequence after power-up

8.2

Mode Register and Extended Mode Registers Operation

For application flexibility, burst length, burst type, CAS Latency, DLL reset function, write recovery

time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS)

command. Additionally, DLL disable function, driver impedance, additive CAS Latency, ODT (On Die

Termination), single-ended strobe and OCD (off chip driver impedance adjustment) are also user

defined variables and must be programmed with an Extended Mode Register Set (EMRS) command.

Contents of the Mode Register (MR) or Extended Mode Registers EMR (1), EMR (2) and EMR (3) can

be altered by re-executing the MRS or EMRS Commands. Even if the user chooses to modify only a

subset of the MR or EMR (1), EMR (2) and EMR (3) variables, all variables within the addressed

register must be redefined when the MRS or EMRS commands are issued.

MRS, EMRS and Reset DLL do not affect array contents, which mean re-initialization including those

can be executed at any time after power-up without affecting array contents.

8.2.1

Mode Register Set Command (MRS)

( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "L", A0 to A12 = Register Data)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It

programs CAS Latency, burst length, burst sequence, test mode, DLL reset, Write Recovery (WR) and

various vendor specific options to make DDR2 SDRAM useful for various applications. The default

value in the Mode Register after power-up is not defined, therefore the Mode Register must be

programmed during initialization for proper operation.

The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into

the mode register. The mode register set command cycle time (tMRD) is required to complete the write

operation to the mode register. The mode register contents can be changed using the same command

and clock cycle requirements during normal operation as long as all banks are in the precharge state.

The mode register is divided into various fields depending on functionality. Burst length is defined by

A[2:0] with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR

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