W9751G6KB-25 datasheet(9/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 9 -

Revision A04

8.

FUNCTIONAL DESCRIPTION

8.1

Power-up and Initialization Sequence

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures

other than those specified may result in undefined operation. The following sequence is required for

Power-up and Initialization.

1. Apply power and attempt to maintain CKE below 0.2 × VDDQ and ODT

*1 at a LOW state (all other

inputs may be undefined.) Either one of the following sequence is required for Power-up.

A. The VDD voltage ramp time must be no greater than 200 mS from when VDD ramps from 300

mV to VDD min; and during the VDD voltage ramp, |VDD -VDDQ|

≤ 0.3 volts.



VDD, VDDL and VDDQ are driven from a single power converter output



VTT is limited to 0.95V max



VREF

*2 tracks VDDQ/2



VDDQ

≥ VREF must be met at all times

B. Voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid

DRAM latch-up. During the ramping of the supply voltages, VDD

≥ VDDL ≥ VDDQ must be

maintained and is applicable to both AC and DC levels until the ramping of the supply voltages

is complete.



Apply VDD/VDDL

*3 before or at the same time as VDDQ



Apply VDDQ

*4 before or at the same time as VTT



VREF

*2 tracks VDDQ/2



VDDQ

≥ VREF must be met at all times



Apply VTT



The VTT voltage ramp time from when VDDQ min is achieved on VDDQ to when VTT min is

achieved on VTT must be no greater than 500 mS

2. Start Clock and maintain stable condition for 200 µS (min.).

3. After stable power and clock (CLK, CLK ), apply NOP or Deselect and take CKE HIGH.

4. Wait minimum of 400 nS then issue precharge all command. NOP or Deselect applied during 400

nS period.

5. Issue an EMRS command to EMR (2). (To issue EMRS command to EMR (2), provide LOW to

BA0, HIGH to BA1.)

6. Issue an EMRS command to EMR (3). (To issue EMRS command to EMR (3), provide HIGH to

BA0 and BA1.)

7. Issue EMRS to enable DLL. (To issue DLL Enable command, provide LOW to A0, HIGH to BA0

and LOW to BA1. And A9=A8=A7=LOW must be used when issuing this command.)

8. Issue a Mode Register Set command for DLL reset. (To issue DLL Reset command, provide HIGH

to A8 and LOW to BA0 and BA1.)

9. Issue a precharge all command.

10. Issue 2 or more Auto Refresh commands.

11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating

parameters without resetting the DLL.)

12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment).

If OCD calibration is not used, EMRS to EMR (1) to set OCD Calibration Default

(A9=A8=A7=HIGH)

followed

by

EMRS

to

EMR

(1)

to

exit

OCD

Calibration

Mode

(A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).

13. The DDR2 SDRAM is now ready for normal operation.

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