W9751G6KB-25 datasheet(74/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

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74 / 87 page

W9751G6KB

Publication Release Date: Sep. 03, 2012

- 74 -

Revision A04

11.10

Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4)

T0

T1

T2

T5

T3

T6

T4

T7

T8

Post CAS

READ A

Post CAS

READ B

NOP

DOUT

A0

DOUT

A1

DOUT

A2

DOUT

A3

DOUT

B0

DOUT

B1

DOUT

B2

CLK

CMD

DQS

DQ's

AL = 2

CL = 3

RL = 5

Note:

The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and

every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are

activated.

11.11

Seamless burst write operation: RL = 5 ( WL = 4, BL = 4)

T0

T1

T2

T5

T3

T6

T4

T7

T8

Post CAS

Write A

Post CAS

Write B

NOP

DIN

A0

DIN

A1

DIN

A2

DIN

A3

DIN

B0

DIN

B1

DIN

B2

CLK

CMD

DQS

DQ's

DIN

B3

WL = RL - 1 = 4

Note:

The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four

clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.

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