W9751G6KB-25 datasheet(64/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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64 / 87 page

W9751G6KB

Publication Release Date: Sep. 03, 2012

- 64 -

Revision A04

DQS

tDS

tDH

tDS

tDH

nominal

slew rate

nominal

slew rate

DC to VREF

region

VDDQ

VIH(ac)min

VIH(dc)min

VREF(dc)

VIL(dc)max

VIL(ac)max

VSS

ΔTF

ΔTR

Hold Slew Rate

Rising Signal =

VREF(dc) - VIL(dc)max

Hold Slew Rate

Falling Signal

=

VIH(dc)min - VREF(dc)

DC to VREF

region

ΔTR

ΔTF

Figure 26

– Illustration of nominal slew rate for tDH (differential DQS, DQS )

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