W9751G6KB-25 datasheet(62/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 62 -

Revision A04

tDS

tDH

tDS

tDH

nominal

slew rate

nominal

slew rate

VREF to AC

region

VDDQ

VIH(ac)min

VIH(dc)min

VREF(dc)

VIL(dc)max

VIL(ac)max

VSS

ΔTF

ΔTR

Setup Slew Rate

Falling Signal

=

VREF(dc) - VIL(ac)max

Setup Slew Rate

Rising Signal

=

VIH(ac)min - VREF(dc)

VREF to AC

region

DQS

ΔTR

ΔTF

Figure 24

– Illustration of nominal slew rate for tDS (differential DQS, DQS )

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