W9751G6KB-25 datasheet(61/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 61 -

Revision A04

45. Slew Rate Measurement Levels:

a)

Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended

signals.

For differential signals (e.g. DQS - DQS ) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS

= + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.

b)

Input slew rate for single ended signals is measured from VREF(dc) to VIH(ac),min for rising edges and from VREF(dc) to

VIL(ac),max for falling edges.

For differential signals (e.g. CLK -

CLK ) slew rate for rising edges is measured from CLK - CLK = - 250 mV to CLK -

CLK = + 500 mV (+ 250 mV to - 500 mV for falling edges).

c)

VID is the magnitude of the difference between the input voltage on CLK and the input voltage on

CLK , or between DQS

and DQS for differential strobe.

46. DDR2 SDRAM output slew rate test load:

Output slew rate is characterized under the test conditions as shown in below figure.

DQ

DQS, DQS

Output

Test point

VTT = VDDQ/2

25

Ω

VDDQ

DUT

Output slew rate test load

47. Differential data strobe:

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS

“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2

SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the

rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the

cross point of DQS and its complement, DQS . This distinction in timing methods is guaranteed by design and characterization.

Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS , must be tied externally

to VSS thro

ugh a 20 Ω to 10 kΩ resistor to insure proper operation.

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