W9751G6KB-25 datasheet(60/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

Download	87 Pages

Scroll/Zoom	100%

Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

Logo

60 / 87 page

W9751G6KB

Publication Release Date: Sep. 03, 2012

- 60 -

Revision A04

44. Data setup and hold time derating.

DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe

DQ

Slew

Rate

(V/nS)

ΔtDS, ΔtDH Derating Values for DDR2-667, DDR2-800 and DDR2-1066 (All units in „pS‟; the note applies to

the entire table)

DQS/

DQS Differential Slew Rate

4.0 V/nS

3.0 V/nS

2.0 V/nS

1.8 V/nS

1.6 V/nS

1.4 V/nS

1.2 V/nS

1.0 V/nS

0.8 V/nS

ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH

2.0

100

45

100

45

100

45

-

1.5

67

21

67

21

67

21

79

33

-

1.0

0

12

24

-

0.9

-

-5

-14

-5

-14

7

-2

19

10

31

22

-

0.8

-

-13

-31

-1

-19

11

-7

23

5

35

17

-

0.7

-

-10

-42

2

-30

14

-18

26

-6

38

6

-

0.6

-

-10

-59

2

-47

14

-35

26

-23

38

-11

0.5

-

-24

-89

-12

-77

0

-65

12

-53

0.4

-

-52

-140

-40

-128

-28

-116

For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and

tDH(base) value to the ΔtDS and ΔtDH derating value respectively. Example: tDS (total setup time) = tDS(base) + ΔtDS.

Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first

crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of

VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between

shaded „VREF(dc) to AC region‟, use nominal slew rate for derating value. See Figure 24 Illustration of nominal slew rate for

tDS (differential DQS, DQS ).

If the actual signal is later than the

nominal slew rate line anywhere between shaded „VREF(dc) to AC region‟, the slew rate of a

tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 25 Illustration of tangent line

for tDS (differential DQS, DQS ).

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first

crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of

VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between

shaded

„DC level to VREF(dc) region‟, use nominal slew rate for derating value. See Figure 26 Illustration of nominal slew rate

for tDH (differential DQS, DQS ).

If the actual signal is earlier than the nominal slew rate line anyw

here between shaded „DC to VREF(dc) region‟, the slew rate of

a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 27 Illustration of

tangent line for tDH (differential DQS, DQS ).

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at

the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).

For slew rates in between the values listed in above DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential

data strobe table, the derating values may be obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

Similar Part No. - W9751G6KB-25

Manufacturer	Part #	Datasheet	Description
Winbond	W9751G6KB	1Mb / 87P	8M ??4 BANKS ??16 BIT DDR2 SDRAM
Microchip Technology	W9751G6KB25I	1Mb / 56P	SAMA5D2 System in Package (SIP) MPU with up to 1 Gbit DDR2 SDRAM or 2 Gbit LPDDR2 SDRAM 2021

More results

Similar Description - W9751G6KB-25

Manufacturer	Part #	Datasheet	Description
Elite Semiconductor Mem...	M13S128324A-2M	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S5121632A-2S	705Kb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S2561616A-2S	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9412G2IB4	832Kb / 50P	Double Data Rate architecture; two data transfers per clock cycle
Winbond	W9412G6JH-5	1Mb / 53P	Double Data Rate architecture; two data transfers per clock cycle
Elite Semiconductor Mem...	M13S2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Elite Semiconductor Mem...	M13L32321A-2G	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W631GG6KB-15	3Mb / 158P	Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Mem...	M13L2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W972GG6JB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle

More results

W9751G6KB-25 Datasheet(PDF) 60 Page - Winbond

W9751G6KB-25 Datasheet(HTML) 60 Page - Winbond

Similar Part No. - W9751G6KB-25

Similar Description - W9751G6KB-25

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

Datasheet Download

Link URL