W9751G6KB-25 datasheet(58/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 58 -

Revision A04

tIS

tIH

tIS

tIH

nominal

slew rate

nominal

slew rate

DC to VREF

region

VDDQ

VIH(ac)min

VIH(dc)min

VREF(dc)

VIL(dc)max

VIL(ac)max

VSS

ΔTF

ΔTR

Hold Slew Rate

Rising Signal

=

VREF(dc) - VIL(dc)max

Hold Slew Rate

Falling Signal =

VIH(dc)min - VREF(dc)

DC to VREF

region

CLK

ΔTR

ΔTF

Figure 22

– Illustration of nominal slew rate for tIH

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