W9751G6KB-25 datasheet(56/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 56 -

Revision A04

CLK

tIS

tIH

tIS

tIH

nominal

slew rate

nominal

slew rate

VREF to AC

region

VDDQ

VIH(ac)min

VIH(dc)min

VREF(dc)

VIL(dc)max

VIL(ac)max

VSS

ΔTF

ΔTR

Setup Slew Rate

Falling Signal

=

VREF(dc) - VIL(ac)max

Setup Slew Rate

Rising Signal

=

VIH(ac)min - VREF(dc)

VREF to AC

region

ΔTF

ΔTR

Figure 20

– Illustration of nominal slew rate for tIS

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