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W9751G6KB-25 Datasheet(PDF) 51 Page - Winbond |
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W9751G6KB-25 Datasheet(HTML) 51 Page - Winbond |
51 / 87 page W9751G6KB Publication Release Date: Sep. 03, 2012 - 51 - Revision A04 30. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters'. The jitter specified is a random jitter meeting a Gaussian distribution. Input clock-Jitter specifications parameters for DDR2-667, DDR2-800 and DDR2-1066 PARAMETER SYMBOL DDR2-667 DDR2-800 DDR2-1066 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Clock period jitter tJIT(per) -125 125 -100 100 -90 90 pS Clock period jitter during DLL locking period tJIT(per,lck) -100 100 -80 80 -80 80 pS Cycle to cycle clock period tJIT(cc) -250 250 -200 200 -180 180 pS Cycle to cycle clock period jitter during DLL locking period tJIT(cc,lck) -200 200 -160 160 -160 160 pS Cumulative error across 2 cycles tERR(2per) -175 175 -150 150 -132 132 pS Cumulative error across 3 cycles tERR(3per) -225 225 -175 175 -157 157 pS Cumulative error across 4 cycles tERR(4per) -250 250 -200 200 -175 175 pS Cumulative error across 5 cycles tERR(5per) -250 250 -200 200 -188 188 pS Cumulative error across n cycles, n = 6 ... 10, inclusive tERR(6-10per) -350 350 -300 300 -250 250 pS Cumulative error across n cycles, n = 11 ... 50, inclusive tERR(11-50per) -450 450 -450 450 -425 425 pS Duty cycle jitter tJIT(duty) -125 125 -100 100 -75 75 pS Definitions: - tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window. tCK(avg) = N j j tCK 1 / N where N = 200 - tCH(avg) and tCL(avg) tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses. tCH(avg) = N j j tCH 1 / (N × tCK(avg)) where N = 200 tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses. tCL(avg) = N j j tCL 1 / (N × tCK(avg)) where N = 200 |
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