W9751G6KB-25 datasheet(49/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

Download	87 Pages

Scroll/Zoom	100%

Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

Logo

49 / 87 page

W9751G6KB

Publication Release Date: Sep. 03, 2012

- 49 -

Revision A04

DQS

tDS(base) tDH(base)

VDDQ

VIH(ac) min

VIH(dc) min

VREF(dc)

VIL(dc) max

VIL(ac) max

VSS

tDS(ref)

tDH(ref)

tDS(ref)

tDH(ref)

Logic levels

VREF levels

Figure 19

– Differential input waveform timing – tDS and tDH

18. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active

power down exit timing. tXARDS is expected to be used for slow active power down exit timing.

19. AL = Additive Latency.

20. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time

max is when the ODT resistance is fully on. Both are measure from tAOND, which is interpreted differently per speed bin.

For DDR2-667/800/1066, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual

input clock edges.

21. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high

impedance. Both are measured from tAOFD, which is interpreted as 0.5 x tCK(avg) [nS] after the second trailing clock edge

counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.

For DDR2-667/800: If tCK(avg) = 3 nS is assumed, tAOFD is 1.5 nS (= 0.5 x 3 nS) after the second trailing clock

edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.

For DDR2-1066: tAOFD is 0.9375 [nS] (= 0.5 x 1.875 [nS]) after the second trailing clock edge counting from the

clock edge that registered a first ODT LOW and by counting the actual input clock edges.

22. The clock frequency is allowed to change during Self Refresh mode or precharge power-down mode. In case of clock

frequency change during precharge power-down, a specific procedure is required as described in section 8.10.

23. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM /

tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied.

Examples:

The device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are

met. This means: For DDR2-667 5-5-5, of which tRP = 15nS, the device will support tnRP = RU{tRP / tCK(avg)} = 5,

i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm+5

is valid even if (Tm+5 - Tm) is less than 15nS due to input clock jitter. For DDR2-1066 7-7-7, of which tRP = 13.125

nS, the device will support tnRP = RU{tRP / tCK(avg)} = 7, i.e. as long as the input clock jitter specifications are met,

Precharge command at Tm and Active command at Tm+7 is valid even if (Tm+7 - Tm) is less than 13.125 nS due to

input clock jitter.

24. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [pS] / tCK(avg) [pS] }, where WR is the value programmed in the

mode register set and RU stands for round up.

Example:

For DDR2-1066 7-7-7 at tCK(avg) = 1.875 nS with WR programmed to 8 nCK, tDAL = 8 + RU{13.125 nS / 1.875

nS} [nCK] = 8 + 7 [nCK] = 15 [nCK].

Similar Part No. - W9751G6KB-25

Manufacturer	Part #	Datasheet	Description
Winbond	W9751G6KB	1Mb / 87P	8M ??4 BANKS ??16 BIT DDR2 SDRAM
Microchip Technology	W9751G6KB25I	1Mb / 56P	SAMA5D2 System in Package (SIP) MPU with up to 1 Gbit DDR2 SDRAM or 2 Gbit LPDDR2 SDRAM 2021

More results

Similar Description - W9751G6KB-25

Manufacturer	Part #	Datasheet	Description
Elite Semiconductor Mem...	M13S128324A-2M	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S5121632A-2S	705Kb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S2561616A-2S	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9412G2IB4	832Kb / 50P	Double Data Rate architecture; two data transfers per clock cycle
Winbond	W9412G6JH-5	1Mb / 53P	Double Data Rate architecture; two data transfers per clock cycle
Elite Semiconductor Mem...	M13S2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Elite Semiconductor Mem...	M13L32321A-2G	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W631GG6KB-15	3Mb / 158P	Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Mem...	M13L2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W972GG6JB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle

More results

W9751G6KB-25 Datasheet(PDF) 49 Page - Winbond

W9751G6KB-25 Datasheet(HTML) 49 Page - Winbond

Similar Part No. - W9751G6KB-25

Similar Description - W9751G6KB-25

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

Datasheet Download

Link URL