W9751G6KB-25 datasheet(48/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 48 -

Revision A04

11. There are two sets of values listed for Command/Address input hold time: tIH(base) and tIH(ref). The tIH(ref) value (for

reference only) is equivalent to the baseline value of tIH(base) at VREF when the slew rate is 1.0 V/nS. The baseline value

tIH(base) is the JEDEC defined value, referenced from the input signal crossing at the VIL(dc) level for a rising signal and

VIH(dc) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to

1.0 V/nS, then the baseline values must be derated by adding the values from table tIS/tIH derating values for DDR2-667,

DDR2-800 and DDR2-1066 (page 55).

12. The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this

parameter, but system performance (bus turnaround) will degrades accordingly.

13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as

well as output Slew Rate mismatch between DQS /

DQS and associated DQ in any given cycle.

14. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is

no longer driving (tRPST), or begins driving (tRPRE). Figure 18 shows a method to calculate these points when the device

is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage

measurement points are not critical as long as the calculation is consistent.

15. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a

specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ). Figure 18

shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the

signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is

consistent. tLZ(DQ) refers to tLZ

of the DQ‟s and tLZ(DQS) refers to tLZ of the (UDQS, LDQS, UDQS and LDQS ) each

treated as single-ended signal.

VOH - x mV

VTT - 2x mV

VTT - x mV

VOH - 2x mV

VOL + 2x mV

VOL + x mV

VTT + x mV

VTT + 2x mV

tRPST end point

tRPRE begin point

tHZ,tRPST end point = 2 x T1 - T2

tLZ,tRPRE begin point = 2 x T1 - T2

tHZ

T1 T2

tLZ

T1 T2

Figure 18

– Method for calculating transitions and endpoints

16. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0. There are two sets of values listed for DQ and

DM input setup time: tDS(base) and tDS(ref). The tDS(ref) value (for reference only) is equivalent to the baseline value

tDS(base) at VREF when the slew rate is 2.0 V/nS, differentially. The baseline value tDS(base) is the JEDEC defined value,

referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and

from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the

device under test. DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. See Figure 19. If the

differential DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from

table of DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe (page 60).

17. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0. There are two sets of values listed for DQ and

DM input hold time: tDH(base) and tDH(ref). The tDH(ref) value (for reference only) is equivalent to the baseline value

tDH(base) at VREF when the slew rate is 2.0 V/nS, differentially. The baseline value tDH(base) is the JEDEC defined value,

referenced from the differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and

from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied to the

device under test. DQS,

DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. See Figure 19. If the

differential DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from

table of DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe (page 60).

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