W9751G6KB-25 datasheet(47/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 47 -

Revision A04

Notes:

1.

All voltages are referenced to VSS.

2.

Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage

levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ODT is

disabled for all measurements that are not ODT-specific.

3.

AC timing reference load:

DQ

DQS, DQS

Output

Timing

reference

point

VTT = VDDQ/2

25

Ω

VDDQ

DUT

Figure 16

– AC timing reference load

4.

This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min)

have been satisfied.

5.

If refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ

can be executed.

6.

This is an optional feature. For detailed information, please refer to

“Operating Temperature Condition” section 10.2 in

this data sheet.

7.

tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the

valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not

transition from its valid level during the time period of tIS + 2 x tCK + tIH.

8.

A minimum of two clocks (2 * nCK) is required irrespective of operating frequency.

9.

tWTR is at least two clocks (2 * nCK) independent of operation frequency.

10. There are two sets of values listed for Command/Address input setup time: tIS(base) and tIS(ref). The tIS(ref) value (for

reference only) is equivalent to the baseline value of tIS(base) at VREF when the slew rate is 1.0 V/nS. The baseline value

tIS(base) is the JEDEC defined value, referenced from the input signal crossing at the VIH(ac) level for a rising signal and

VIL(ac) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to

1.0 V/nS, then the baseline values must be derated by adding the values from table of tIS/tIH derating values for DDR2-667,

DDR2-800 and DDR2-1066 (page 55).

CLK

tIS(base)

tIH(base)

tIS(base)

tIH(base)

VDDQ

VIH(ac) min

VIH(dc) min

VREF(dc)

VIL(dc) max

VIL(ac) max

VSS

tIS(ref)

tIH(ref)

tIS(ref)

tIH(ref)

Logic levels

VREF levels

Figure 17

– Differential input waveform timing – tIS and tIH

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