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W9751G6KB-25 Datasheet(PDF) 43 Page - Winbond |
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W9751G6KB-25 Datasheet(HTML) 43 Page - Winbond |
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43 / 87 page  W9751G6KB Publication Release Date: Sep. 03, 2012 - 43 - Revision A04 10.11 AC Characteristics 10.11.1 AC Characteristics and Operating Condition for -18 speed grade Notes: 1-3 and 45-47 apply to the entire table SYM. SPEED GRADE DDR2-1066 (-18) UNIT 25 NOTES Bin(CL-tRCD-tRP) 7-7-7 PARAMETER MIN. MAX. tRCD Active to Read/Write Command Delay Time 13.125 nS 23 tRP Precharge to Active Command Period 13.125 nS 23 tRC Active to Ref/Active Command Period 58.125 nS 23 tRAS Active to Precharge Command Period 45 70000 nS 4,23 tRFC Auto Refresh to Active/Auto Refresh command period 105 nS 5 tREFI Average periodic refresh Interval 0°C ≤ TCASE ≤ 85°C 7.8 μS 5 85°C < TCASE ≤ 95°C 3.9 μS 5,6 tCCD CAS to CAS command delay 2 nCK tCK(avg) Average clock period tCK(avg) @ CL=4 3.75 7.5 nS 30,31 tCK(avg) @ CL=5 3 7.5 nS 30,31 tCK(avg) @ CL=6 2.5 7.5 nS 30,31 tCK(avg) @ CL=7 1.875 7.5 nS 30,31 tCH(avg) Average clock high pulse width 0.48 0.52 tCK(avg) 30,31 tCL(avg) Average clock low pulse width 0.48 0.52 tCK(avg) 30,31 tAC DQ output access time from CLK/ CLK -350 350 pS 35 tDQSCK DQS output access time from CLK / CLK -325 325 pS 35 tDQSQ DQS-DQ skew for DQS & associated DQ signals 175 pS 13 tCKE CKE minimum high and low pulse width 3 nCK 7 tRRD Active to active command period for 2KB page size 10 nS 8,23 tFAW Four Activate Window for 2KB page size 45 nS 23 tWR Write recovery time 15 nS 23 tDAL Auto-precharge write recovery + precharge time WR + tnRP nCK 24 tWTR Internal Write to Read command delay 7.5 nS 9,23 tRTP Internal Read to Precharge command delay 7.5 nS 4,23 tIS (base) Address and control input setup time 125 pS 10,26, 40,42,43 tIH (base) Address and control input hold time 200 pS 11,26, 40,42,43 tIS (ref) Address and control input setup time 325 pS 10,26, 40,42,43 tIH (ref) Address and control input hold time 325 pS 11,26, 40,42,43 tIPW Address and control input pulse width for each input 0.6 tCK(avg) tDQSS DQS latching rising transitions to associated clock edges -0.25 0.25 tCK(avg) 28 tDSS DQS falling edge to CLK setup time 0.2 tCK(avg) 28 tDSH DQS falling edge hold time from CLK 0.2 tCK(avg) 28 tDQSH DQS input high pulse width 0.35 tCK(avg) tDQSL DQS input low pulse width 0.35 tCK(avg) |
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Similar Description - W9751G6KB-25 |
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