W9751G6KB-25 datasheet(39/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 39 -

Revision A04

10.7

Capacitance

SYM.

PARAMETER

MIN.

MAX.

UNIT

CCK

Input Capacitance , CLK and

CLK

1.0

2.0

pF

CDCK

Input Capacitance delta , CLK and

CLK



0.25

pF

CI

input Capacitance, all other input-only pins

1.0

1.75

pF

CDI

Input Capacitance delta, all other input-only pins



0.25

pF

CIO

Input/output Capacitance, DQ, LDM, UDM, LDQS,

LDQS , UDQS, UDQS

2.5

3.5

pF

CDIO

Input/output Capacitance delta, DQ, LDM, UDM,

LDQS,

LDQS , UDQS, UDQS



0.5

pF

10.8

Leakage and Output Buffer Characteristics

SYM.

PARAMETER

MIN.

MAX.

UNIT

NOTES

IIL

Input Leakage Current

(

0V

≤ VIN ≤ VDD)

-2

2

µA

1

IOL

Output Leakage Current

(Output disabled,

0V

≤ VOUT ≤ VDDQ)

-5

5

µA

2

VOH

Minimum Required Output Pull-up

VTT + 0.603



V

VOL

Maximum Required Output Pull-down



VTT - 0.603

V

VOTR

Output Timing Measurement Reference Level

0.5 x VDDQ



V

3

IOH(dc)

Output Minimum Source DC Current

-13.4



mA

4, 6

IOL(dc)

Output Minimum Sink DC Current

13.4



mA

5, 6

Notes:

1. All other pins not under test = 0 V.

2. DQ, LDQS, LDQS , UDQS, UDQS are disabled and ODT is turned off.

3. The VDDQ of the device under test is referenced.

4. VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT - VDDQ)/IOH

must be less than 21 Ω for values of VOUT between VDDQ and VDDQ -

0.28V.

5. VDDQ = 1.7 V; VOUT = 0.28V. VOUT/IOL

must be less than 21 Ω for values of VOUT between 0 V and 0.28V.

6. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 3 and 4. They are used to test drive current

capability to ensure VIHmin plus a noise margin and VILmax minus a noise margin are delivered to an SSTL_18 receiver.

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