W9412G2IB4 datasheet(30/50 Pages) WINBOND

Part #	W9412G2IB4

Description	Double Data Rate architecture; two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9412G2IB

Publication Release Date: Aug. 30, 2010

- 30 -

Revision A06

V SWING (MAX)

VDDQ

VSS

T

VIH min (AC)

VREF

VIL max (AC)

SLEW = (VIHmin (AC) - VILmax (AC)) / T

Output

50 Ω

VTT

Timing Reference Load

Output

V(out)

30pF

Notes:

(1)

Conditions outside the limits listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

(2)

All voltages are referenced to VSS, VSSQ. ( 2.5V

±0.1V for DDR500)

(3)

Peak to peak AC noise on VREF may not exceed

±2% VREF(DC).

(4)

VOH = 1.95V, VOL = 0.35V

(5)

VOH = 1.9V, VOL = 0.4V

(6)

The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V.

The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V.

(7)

These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values

of tCK and tRC.

(8)

VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set

equal to VREF and must track variations in the DC level of VREF.

(9)

These parameters depend on the output loading. Specified values are obtained with the output open.

(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed

slope.

(11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to

the nearest decimal place.

(i.e., tDQSS = 0.75

× tCK, tCK = 7.5 nS, 0.75 × 7.5 nS = 5.625 nS is rounded up to 5.6 nS.)

(12) VX is the differential clock cross point voltage where input timing measurement is referenced.

(13) VID is magnitude of the difference between CLK input level and CLK input level.

(14) VISO means {VICK(CLK)+VICK( CLK )}/2.

(15) Refer to the figure below.

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