W9412G2IB4 datasheet(27/50 Pages) WINBOND

Part #	W9412G2IB4

Description	Double Data Rate architecture; two data transfers per clock cycle

Download	50 Pages

Scroll/Zoom	100%

Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

Logo

27 / 50 page

W9412G2IB

Publication Release Date: Aug. 30, 2010

- 27 -

Revision A06

9.5 DC Characteristics

MAX.

SYM.

PARAMETER

-4

-5/-5I

-6/-6I

UNIT NOTES

IDD0

Operating current: One Bank Active-Precharge; tRC = tRC min;

tCK = tCK min; DQ, DM and DQS inputs changing twice per

clock cycle; Address and control inputs changing once per

clock cycle

160

150

140

mA

7

IDD1

Operating current: One Bank Active-Read-Precharge; Burst =

2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address

and control inputs changing once per clock cycle.

180

170

160

mA

7, 9

IDD2P

Precharge Power Down standby current: All Banks Idle; Power

down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ,

DQS and DM

30

mA

IDD2N

Idle standby current: CS > VIH min; All Banks Idle; CKE > VIH

min; tCK = tCK min; Address and other control inputs changing

once per clock cycle; Vin > VIH min or Vin < VIL max for DQ,

DQS and DM

45

mA

7

IDD3P

Active Power Down standby current: One Bank Active; Power

down mode; CKE < VIL max; tCK = tCK min

30

mA

IDD3N

Active standby current: CS > VIH min; CKE > VIH min; One

Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM

and DQS inputs changing twice per clock cycle; Address and

other control inputs changing once per clock cycle

60

mA

7

IDD4R

Operating current: Burst = 2; Reads; Continuous burst; One

Bank Active; Address and control inputs changing once per

clock cycle; CL=3; tCK = tCK min; IOUT = 0mA

240

220

200

mA

7, 9

IDD4W

Operating current: Burst = 2; Write; Continuous burst; One

Bank Active; Address and control inputs changing once per

clock cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs

changing twice per clock cycle

270

250

230

mA

7

IDD5

Auto Refresh current: tRC = tRFC min

210

200

190

mA

7

IDD6

Self Refresh current: CKE < 0.2V

3

mA

IDD7

Random Read current: 4 Banks Active Read with activate

every 20nS, Auto-Precharge Read every 20 nS; Burst = 4; tRCD

= 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice per

clock cycle; Address changing once per clock cycle

340

320

300

mA

Similar Part No. - W9412G2IB4

Manufacturer	Part #	Datasheet	Description
Winbond	W9412G2IB	832Kb / 50P	1M 횞 4 BANKS 횞 32 BITS GDDR SDRAM

More results

Similar Description - W9412G2IB4

Manufacturer	Part #	Datasheet	Description
Elite Semiconductor Mem...	M13S128324A-2M	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S5121632A-2S	705Kb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S2561616A-2S	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9412G6JH-5	1Mb / 53P	Double Data Rate architecture; two data transfers per clock cycle
Elite Semiconductor Mem...	M13S2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9751G6KB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Mem...	M13L32321A-2G	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W631GG6KB-15	3Mb / 158P	Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Mem...	M13L2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W972GG6JB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle

More results

W9412G2IB4 Datasheet(PDF) 27 Page - Winbond

W9412G2IB4 Datasheet(HTML) 27 Page - Winbond

Similar Part No. - W9412G2IB4

Similar Description - W9412G2IB4

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL