Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

W9412G2IB4 Datasheet(PDF) 22 Page - Winbond

Part # W9412G2IB4
Description  Double Data Rate architecture; two data transfers per clock cycle
Download  50 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W9412G2IB4 Datasheet(HTML) 22 Page - Winbond

Back Button W9412G2IB4 Datasheet HTML 18Page - Winbond W9412G2IB4 Datasheet HTML 19Page - Winbond W9412G2IB4 Datasheet HTML 20Page - Winbond W9412G2IB4 Datasheet HTML 21Page - Winbond W9412G2IB4 Datasheet HTML 22Page - Winbond W9412G2IB4 Datasheet HTML 23Page - Winbond W9412G2IB4 Datasheet HTML 24Page - Winbond W9412G2IB4 Datasheet HTML 25Page - Winbond W9412G2IB4 Datasheet HTML 26Page - Winbond Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 50 page
background image
W9412G2IB
Publication Release Date: Aug. 30, 2010
- 22 -
Revision A06
8.4 Function Truth Table, continued
CURRENT
STATE
CS RAS CAS
WE
ADDRESS
COMMAND
ACTION
NOTES
H
X
X
X
X
DSL
NOP->Row active after tWR
L
H
H
H
X
NOP
NOP->Row active after tWR
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A8
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A8
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A8
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
Write
Recovering
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
NOP->Enter precharge after
tWR
L
H
H
H
X
NOP
NOP->Enter precharge after
tWR
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A8
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A8
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A8
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
Write
Recovering
with Auto-
precharge
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
NOP->Idle after tRC
L
H
H
H
X
NOP
NOP->Idle after tRC
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
X
READ/WRIT
ILLEGAL
L
L
H
X
X
ACT/PRE/PREA
ILLEGAL
Refreshing
L
L
L
X
X
AREF/SELF/MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
NOP->Row after tMRD
L
H
H
H
X
NOP
NOP->Row after tMRD
L
H
H
L
X
BST
ILLEGAL
L
H
L
X
X
READ/WRIT
ILLEGAL
Mode
Register
Accessing
L
L
X
X
X
ACT/PRE/PREA/ARE
F/SELF/MRS/EMRS
ILLEGAL
Notes
:
1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle.
2. Illegal if any bank is not idle.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
4. Illegal if tRCD is not satisfied.
5. Illegal if tRAS is not satisfied.
6. Must satisfy burst interrupt condition.
7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.
8. Must mask preceding data which don’t satisfy tWR
Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data


Similar Part No. - W9412G2IB4

ManufacturerPart #DatasheetDescription
logo
Winbond
W9412G2IB WINBOND-W9412G2IB Datasheet
832Kb / 50P
   1M 횞 4 BANKS 횞 32 BITS GDDR SDRAM
More results

Similar Description - W9412G2IB4

ManufacturerPart #DatasheetDescription
logo
Elite Semiconductor Mem...
M13S128324A-2M ESMT-M13S128324A-2M Datasheet
1Mb / 48P
   Double-data-rate architecture, two data transfers per clock cycle
M13S5121632A-2S ESMT-M13S5121632A-2S Datasheet
705Kb / 48P
   Double-data-rate architecture, two data transfers per clock cycle
M13S2561616A-2S ESMT-M13S2561616A-2S Datasheet
1Mb / 49P
   Double-data-rate architecture, two data transfers per clock cycle
logo
Winbond
W9412G6JH-5 WINBOND-W9412G6JH-5 Datasheet
1Mb / 53P
   Double Data Rate architecture; two data transfers per clock cycle
logo
Elite Semiconductor Mem...
M13S2561616A-2A ESMT-M13S2561616A-2A Datasheet
1Mb / 49P
   Double-data-rate architecture, two data transfers per clock cycle
logo
Winbond
W9751G6KB-25 WINBOND-W9751G6KB-25 Datasheet
1Mb / 87P
   Double Data Rate architecture: two data transfers per clock cycle
logo
Elite Semiconductor Mem...
M13L32321A-2G ESMT-M13L32321A-2G Datasheet
1Mb / 48P
   Double-data-rate architecture, two data transfers per clock cycle
logo
Winbond
W631GG6KB-15 WINBOND-W631GG6KB-15 Datasheet
3Mb / 158P
   Double Data Rate architecture: two data transfers per clock cycle
logo
Elite Semiconductor Mem...
M13L2561616A-2A ESMT-M13L2561616A-2A Datasheet
1Mb / 49P
   Double-data-rate architecture, two data transfers per clock cycle
logo
Winbond
W972GG6JB-25 WINBOND-W972GG6JB-25 Datasheet
1Mb / 87P
   Double Data Rate architecture: two data transfers per clock cycle
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com