W9412G2IB4 datasheet(15/50 Pages) WINBOND

Part #	W9412G2IB4

Description	Double Data Rate architecture; two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9412G2IB

Publication Release Date: Aug. 30, 2010

- 15 -

Revision A06

resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh

operation.

7.8 Power Down Mode

Two types of Power Down Mode can be performed on the device: Active Power Down Mode and

Precharge Power Down Mode.

When the device enters the Power Down Mode, all input/output buffers are disabled resulting in

low power dissipation (except CKE buffer).

Power Down Mode enter asserting CKE “low” while the device is not running a burst cycle. Taking

CKE “high” can exit this mode. When CKE goes high, a No operation command must be input at

next CLK rising edge. Refer to the diagrams for Power Down Mode.

7.9 Input Clock Frequency Change during Precharge Power Down Mode

DDR SDRAM input clock frequency can be changed under following condition:

DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a

minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency

between minimum and maximum operating frequency specified for the particular speed grade.

During an input clock frequency change, CKE must be held LOW. Once the input clock frequency

is changed, a stable clock must be provided to DRAM before precharge power down mode may be

exited. The DLL must be RESET via EMRS after precharge power down exit. An additional MRS

command may need to be issued to appropriately set CL etc. After the DLL relock time, the DRAM

is ready to operate with new clock frequency.

7.10 Mode Register Operation

The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all

banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to

A11 and BA0, BA1 address inputs.

The Mode Register designates the operation mode for the read or write cycle. The register is

divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode

selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set

the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode

Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented

the extended function (DLL enable/Disable mode).

The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the

Mode Register Set command must be issued before power operation.

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