W9412G2IB4 datasheet(8/50 Pages) WINBOND

Part #	W9412G2IB4

Description	Double Data Rate architecture; two data transfers per clock cycle

Download	50 Pages

Scroll/Zoom	100%

Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

Logo

8 / 50 page

W9412G2IB

Publication Release Date: Aug. 30, 2010

- 8 -

Revision A06

BALL DESCRIPTION, continued

BALL LOCATION PIN NAME

FUNCTION

DESCRIPTION

D4,D6,D7,D9,

E5~E8,F5~F8,G5~

G8,H5~H8,J5~J8,K

4,K9

VSS

Ground

Ground for logic circuit inside DDR SDRAM.

B2,B4,B6,B7,

B9,B11,D2,D11,E3,

E10,F3,F10,H3,H10

,J3,J10

VDDQ

Power ( + 2.5V ) for

I/O buffer

Separated power from VDD, used for output buffer, to

improve noise immunity.

A3,A10,C3~C5,

C8~C10,D5,D8,E4,

E9,F4,F9,G4,G9,H4

,H9,J4,J9

VSSQ

Ground for I/O

buffer

Separated ground from VSS, used for output buffer, to

improve noise immunity.

B3,B10,G3,G10,K1

1,K12,L2,L3,L12,M

2

NC

No Connection

No connection

K8,L9

RFU

No Connection

Reserved for Future Use.

Similar Part No. - W9412G2IB4

Manufacturer	Part #	Datasheet	Description
Winbond	W9412G2IB	832Kb / 50P	1M 횞 4 BANKS 횞 32 BITS GDDR SDRAM

More results

Similar Description - W9412G2IB4

Manufacturer	Part #	Datasheet	Description
Elite Semiconductor Mem...	M13S128324A-2M	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S5121632A-2S	705Kb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S2561616A-2S	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9412G6JH-5	1Mb / 53P	Double Data Rate architecture; two data transfers per clock cycle
Elite Semiconductor Mem...	M13S2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9751G6KB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Mem...	M13L32321A-2G	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W631GG6KB-15	3Mb / 158P	Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Mem...	M13L2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W972GG6JB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle

More results

W9412G2IB4 Datasheet(PDF) 8 Page - Winbond

W9412G2IB4 Datasheet(HTML) 8 Page - Winbond

Similar Part No. - W9412G2IB4

Similar Description - W9412G2IB4

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL