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DM7442 Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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DM7442 Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 4 page 3 www.fairchildsemi.com Absolute Maximum Ratings(Note 1) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Note 2: All typicals are at VCC = 5V, TA = 25°C. Note 3: Not more than one output should be shorted at a time. Note 4: ICC is measured with all outputs open and all inputs grounded. Switching Characteristics at VCC = 5V and TA = 25°C Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range 0 °C to +70°C Storage Temperature Range −65°C to +150°C Symbol Parameter Min Nom Max Units VCC Supply Voltage 4.75 5 5.25 V VIH HIGH Level Input Voltage 2 V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.8 mA IOL LOW Level Output Current 16 mA TA Free Air Operating Temperature 0 70 °C Symbol Parameter Conditions Min Typ Max Units (Note 2) VI Input Clamp Voltage VCC = Min, II = −12 mA −1.5 V VOH HIGH Level VCC = Min, IOH = Max 2.4 3.4 V Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max 0.2 0.4 V Output Voltage VIH = Min, VIL = Max II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA IIH HIGH Level Input Current VCC = Max, VI = 2.4V 40 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA IOS Short Circuit Output Current VCC = Max (Note 3) −18 −55 mA ICC Supply Current VCC = Max (Note 4) 28 56 mA Symbol Parameter Conditions Min Max Units tPHL Propagation Delay Time CL = 15 pF HIGH-to-LOW Level Output RL = 400Ω 25 ns from A, B, C or D through 2 Levels of Logic tPHL Propagation Delay Time HIGH-to-LOW Level Output 30 ns from A, B, C or D through 3 Levels of Logic tPLH Propagation Delay Time LOW-to-HIGH Level Output 25 ns from A, B, C or D through 2 Levels of Logic tPLH Propagation Delay Time LOW-to-HIGH Level Output 30 ns from A, B, C or D through 3 Levels of Logic |
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