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AB28F800B5T80 Datasheet(PDF) 32 Page - Intel Corporation |
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AB28F800B5T80 Datasheet(HTML) 32 Page - Intel Corporation |
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32 / 44 page  28F200B5, 28F004/400B5, 28F800B5 E 32 PRELIMINARY NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, T = +25 °C. These currents are valid for all product versions (packages and speeds). 2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases and word/byte program operations are inhibited when VPP = VPPLK, and not guaranteed in the range between VPPH1 and VPPLK. 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces I CCR to less than 1 mA typical, in static operation. 6. CMOS Inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH. TEST POINTS INPUT OUTPUT 1.5 3.0 0.0 1.5 0599-10 NOTE: AC test inputs are driven at 3.0 V for a logic “1” and 0.0 V for a logic “0.” Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) <10 ns. Figure 11. High Speed Test Waveform TEST POINTS INPUT OUTPUT 2.0 0.8 0.8 2.0 2.4 0.45 0599-11 NOTE: AC test inputs driven at VOH (2.4 VTTL) for logic “1” and VOL (0.45 VTTL) for logic “0.” Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL) . Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. Figure 12. Standard Test Waveform |
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