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AB28F800B5T80 Datasheet(PDF) 25 Page - Intel Corporation |
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AB28F800B5T80 Datasheet(HTML) 25 Page - Intel Corporation |
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25 / 44 page  E 28F200B5, 28F004/400B5, 28F800B5 25 PRELIMINARY 4.1.3 STANDBY POWER When CE# is at a logic-high level (VIH), and the device is not programming or erasing, the memory enters in standby mode, which disables much of the device’s circuitry and substantially reduces power consumption. Outputs (DQ0–DQ15 or DQ0–DQ7) are placed in a high-impedance state independent of the status of the OE# signal. When CE# is at logic- high level during program or erase operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. 4.1.4 DEEP POWER-DOWN MODE The 5 Volt Boot Block Flash family supports a low typical ICCD in deep power-down mode, which turns off all circuits to save power. This mode is activated by the RP# pin when it is at a logic-low (GND ± 0.2 V). Note: BYTE# pin must be at CMOS levels to meet the ICCD specification. During read modes, the RP# pin going low de- selects the memory and places the output drivers in a high impedance state. Recovery from the deep power-down state, requires a minimum access time of tPHQV. RP# transitions to VIL, or turning power off to the device will clear the status register. During an program or erase operation, RP# going low for time tPLPH will abort the operation, but the location’s memory contents will no longer valid and additional timing must be met. See Section 3.1.5 and Figure 15 and Table 10 for additional information. 4.2 Power-Up/Down Operation The device protects against accidental block erasure or programming during power transitions. Power supply sequencing is not required, so either VPP or VCC can power-up first. The CUI defaults to the read mode after power-up, but the system must drop CE# low or present an address to receive valid data at the outputs. A system designer must guard against spurious writes when VCC voltages are above VLKO and VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. Additionally, alteration of memory can only occur after successful completion of a two-step command sequences. The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 4.2.1 RP# CONNECTED TO SYSTEM RESET Using RP# properly during system reset is important with automated program/erase devices because the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization would not occur because the flash memory may in a mode other than Read Array. Intel’s Flash memories allow proper CPU initialization following a system reset by connecting the RP# pin to the same RESET# signal that resets the system CPU. 4.3 Board Design 4.3.1 POWER SUPPLY DECOUPLING Flash memory’s switching characteristics require careful decoupling methods. System designers should consider three supply current issues: standby current levels (ICCS), active current levels (ICCR), and transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between VCC and GND, and between VPP and GND. These high-frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 4.3.2 VPP TRACE ON PRINTED CIRCUIT BOARDS In-system updates to the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. Since the VPP pin supplies the current for programming and erasing, it should have similar trace widths and layout considerations as given to the VCC power supply trace. Adequate VPP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots. |
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