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AB28F800B5T80 Datasheet(PDF) 22 Page - Intel Corporation |
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AB28F800B5T80 Datasheet(HTML) 22 Page - Intel Corporation |
22 / 44 page 28F200B5, 28F004/400B5, 28F800B5 E 22 PRELIMINARY SR.7 = 0 1 Start Write 20H, Block Address Write D0H and Block Address Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE 1 0 Read Status Register Data (See Above) 1 0 Read Status Register V Range Error PP Suspend Erase Suspend Erase Loop YES NO 1 0 Command Sequence Error SR.3 = SR.5 = SR.4,5 = Block Erase Error Bus Operation Command Comments Standby Check SR.4,5 Both 1 = Command Sequence Error Standby Check SR.3 1 = V Low Detect SR.3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. SR.5 is only cleared by the Clear Status Register Command, in cases where multiple blocks are erase before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Check SR.5 1 = Block Erase Error Standby Bus Operation Command Comments Write Write Erase Setup Read Data = 20H Addr = Within Block to be Erased Check SR.7 1 = WSM Ready 0 = WSM Busy Repeat for subsequent block erasures. Full Status Check can be done after each block erase, or after a sequence of block erasures. Write FFH after the last operation to reset device to read array mode. Status Register Data Toggle CE# or OE# to Update Status Register Standby Erase Confirm Data = D0H Addr = Within Block to be Erased Block Erase Successful PP 0599-08 Figure 9. Automated Block Erase Flowchart |
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