E

28F200B5, 28F004/400B5, 28F800B5

19

PRELIMINARY

Table 6. Command Codes and Descriptions (Continued)

Code

Device Mode

Description

50

Clear Status

Register

The WSM can only set the program status and erase status bits in the status

register to “1”; it cannot clear them to “0.”

The status register operates in this fashion for two reasons. The first is to give the

host CPU the flexibility to read the status bits at any time. Second, when

programming a string of bytes, a single status register query after programming the

string may be more efficient, since it will return the accumulated error status of the

entire string. See Section 3.2.3.1.

90

Intelligent

Identifier

Puts the device into the intelligent identifier read mode, so that reading the device

Table 7. Command Bus Definitions

First Bus Cycle

Second Bus Cycle

Command

Note

Oper

Addr

Data

Oper

Addr

Data

Read Array

Write

X

FFH

Intelligent Identifier

2,4

Write

X

90H

Read

IA

IID

Read Status Register

3

Write

X

70H

Read

X

SRD

Clear Status Register

3

Write

X

50H

Word/Byte Program

6,7

Write

PA

40H/10H

Write

PA

PD

Block Erase/Confirm

5

Write

BA

20H

Write

BA

D0H

Erase Suspend

Write

X

B0H

Erase Resume

Write

X

D0H

ADDRESS

DATA

BA = Block Address

SRD = Status Register Data

IA = Identifier Address

IID = Identifier Data

PA = Program Address

PD = Program Data

X = Don’t Care

NOTES:

1.

Bus operations are defined in Tables 3 and 4.

2.

3.

SRD - Data read from Status Register.

4.

IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and

device codes.

5.

BA = Address within the block being erased.

6.

PA = Address to be programmed. PD = Data to be programmed at location PA.

7.

Either 40H or 10H commands is valid.

8.

draw.