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AOZ7111 Datasheet(PDF) 12 Page - Alpha & Omega Semiconductors |
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AOZ7111 Datasheet(HTML) 12 Page - Alpha & Omega Semiconductors |
12 / 15 page ![]() AOZ7111 Rev. 1.0 January 2013 www.aosmd.com Page 12 of 15 Application Information Alpha and Omega Semiconductor provides an EXCEL based design tool, an application note and a demonstration board to help the design of AOZ7111 and reduce the R&D cycle time. All the tools can be download from: www.aosmd.com. PCB Layout Guide The following are good PCB layout guideline for a PFC stage: 1. To keep the IC GND pin as clean as possible, the power stage ground and the signal ground must be separated. 2. The PFC MOSFET gate drive loop path should be minimized. 3. Minimize the trace length to INV pin. Since the feedback node is high impedance the trace from the output resistor divider to INV pin should be as short as possible. 4. Switching current sense (CS pin) is very important for the stable operation of PFC stage. Normally, a RC filter is recommended to reduce the noise applied to the CS pin. 5. The VCC decoupling capacitor CVCC need to be placed close to IC VCC and GND pin as much as possible. Figure 7. Recommended PCB Layout |
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