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NCP1608 Datasheet(PDF) 17 Page - ON Semiconductor |
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NCP1608 Datasheet(HTML) 17 Page - ON Semiconductor |
17 / 24 page ![]() NCP1608 http://onsemi.com 17 Figure 37. Ct Pin Noise Induced On Time Reduction and Pulse Skipping Noise Induced Voltage Spike DRV Remains Off DRV is Not Exceeded 0 V ton tstart ton(loop) VCL(NEG) VZCD(TRIG) VZCD VZCD(ARM) VZCD(ARM) VCt(off) VCt VControl Ct(offset) Low VControl Voltage Low VCt(off) Voltage VControl − Ct(offset) The wide control range of the NCP1608 increases VControl and VCt(off) in comparison to devices with less control range. Figure 38 compares VCt(off) of the NCP1608 to a device with a 3 V control range for an application with the following parameters: Pout = 250 W L = 200 mH h = 92% VacLL = 85 Vac VacHL = 265 Vac Figure 38 shows that VCt(off) of the NCP1608 is 50% larger than the 3 V control range device. The 50% increase enables the NCP1608 to prevent inadvertent skipping at high input voltages and high output power. Pout, OUTPUT POWER (W) 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 25 75 125 175 225 275 Figure 38. Comparison of Ct Charging Threshold vs. Output Power NCP1608 Vin = 265 Vac 3 V Control Range Startup Generally, a resistor connected between the rectified ac line and VCC charges the VCC capacitor to VCC(on). The low startup current consumption (< 35 mA) enables minimized standby power dissipation and reduced startup durations. When VCC exceeds VCC(on), the internal references and logic of the NCP1608 are enabled. The controller includes an undervoltage lockout (UVLO) feature that ensures that the NCP1608 is enabled until VCC decreases to less than VCC(off). This hysteresis ensures sufficient time for the auxiliary winding to supply VCC (Figure 39). Figure 39. Typical VCC Startup Waveform VCC VCC(on) VCC(off) When the PFC pre-converter is loaded by a switch−mode power supply (SMPS), it is generally preferable for the SMPS controller to startup first. The SMPS then supplies the NCP1608 VCC. Advanced controllers, such as the NCP1230 or NCP1381, control the enabling of the PFC stage (see Figure 40) and achieve optimal system performance. This sequence eliminates the startup resistors and improves the standby power dissipation of the system. |
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