NCP1608_10 datasheet(13/24 Pages) ONSEMI

Part #	NCP1608

Description	Critical Conduction Mode PFC Controller Utilizing a Transconductance Error Amplifier

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NCP1608

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A resistor divider (Rout1 and Rout2) scales down the boost

output voltage (Vout) and is connected to the FB pin. If the

output voltage is less than the target output voltage, then

VFB is less than VREF and the EA increases the control

voltage (VControl). This increases the on time of the driver,

which increases the power delivered to the output. The

increase in delivered power causes Vout to increase until the

target output voltage is achieved. Alternatively, if Vout is

greater than the target output voltage, then VControl

decreases to cause the on time to decrease until Vout

decreases to the target output voltage. This cause and effect

regulates Vout so that the scaled down Vout that is applied

to FB through Rout1 and Rout2 is equal to VREF. The

presence of RFB (4.6 MW typical value) for FPP is included

in the divider network calculation.

The output voltage is set using Equation 2:

Vout + VREF @ Rout1 @

Rout2 ) RFB

Rout2 @ RFB

) 1

(eq. 2)

The divider network bias current is selected to optimize

the tradeoff of noise immunity and power dissipation. Rout1

is calculated using the bias current and output voltage using

Equation 3:

Rout1 +

Vout

Ibias(out)

(eq. 3)

Where Ibias(out) is the output divider network bias current.

Rout2 is dependent on Vout, Rout1, and RFB.

Rout2 is calculated using Equation 4:

Rout2 +

Rout1 @ RFB

RFB @

Vout

V

REF

* 1 * Rout1

(eq. 4)

The PFC stage consumes a sinusoidal current from a

sinusoidal line voltage. The converter provides the load

with a power that matches the average demand only. The

output capacitor (Cbulk) compensates for the difference

between the delivered power and the power consumed by

the load. When the power delivered to the load is less than

the power consumed by the load, Cbulk discharges. When

the delivered power is greater than the power consumed by

the load, Cbulk charges to store the excess energy. The

situation is depicted in Figure 30.

Figure 30. Output Voltage Ripple for a Constant Output Power

Vout

Pout

Iac

Vac

Due to the charging/discharging of Cbulk, Vout contains

a ripple at a frequency of either 100 Hz (for a 50 Hz line

frequency in Europe) or 120 Hz (for a 60 Hz line frequency

in the USA). The Vout ripple is attenuated by the regulation

loop to ensure VControl is constant during the ac line cycle

for the proper shaping of the line current. To ensure VControl

is constant during the ac line cycle, the loop bandwidth is

typically set below 20 Hz. A type 1 compensation network

consists of a capacitor (CCOMP) connected between the

Control and ground pins (see Figure 1). The capacitor value

that sets the loop bandwidth is calculated using Equation 5:

CCOMP +

gm

2 @ p @ fCROSS

(eq. 5)

Where fCROSS is the crossover frequency and gm is the

error amplifier transconductance. The crossover frequency

is set below 20 Hz.

On Time Sequence

The switching pattern consists of constant on times and

variable off times for a given rms input voltage and output

load. The NCP1608 controls the on time with the capacitor

connected to the Ct pin. A current source charges the Ct

capacitor to a voltage derived from the Control pin voltage

(VCt(off)). VCt(off) is calculated using Equation 6:

VCt(off) + VControl − Ct(offset) +

2 @ Pout @ L @ Icharge

h @ Vac2 @ Ct

(eq. 6)

When VCt(off) is reached, the drive turns off (Figure 31).

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