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AD9801 Datasheet(PDF) 4 Page - Analog Devices

Part # AD9801
Description  CCD Signal Processor For Electronic Cameras
Download  12 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9801 Datasheet(HTML) 4 Page - Analog Devices

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AD9801
–4–
REV. 0
Pin No.
Pin Name
Type
Description
1
ADVSS
P
Analog Ground
2–11
D0–D9
DO
Digital Data Outputs
12
DRVDD
P
+3 V Digital Driver Supply
13
DRVSS
P
Digital Driver Ground
14
DSUBST
P
Digital Substrate
15
DVSS
P
Digital Ground
16
ADCCLK
DI
ADC Sample Clock Input
17
DVDD
P
+3 V Digital Supply
18
STBY
DI
Power down (Active HIGH)
19
PBLK
DI
Pixel Blanking (Active LOW)
20
CLPOB
DI
Black Level Restore Clamp (Active LOW)
21
SHP
DI
Reference Sample Clock Input
22
SHD
DI
Data Sample Clock Input
23
CLPDM
DI
Input Clamp (Active Low)
24
DVSS
DI
Digital Ground
25
CCDBYP2
AO
CCD Bypass (Decouple to Analog Ground Through 0.1
µF)
26
DIN
AI
CDS Input (Tie to Pin 27 and AC-Couple to CCD Output Through 0.1
µF)
27
PIN
AI
CDS Input (See Above)
28
CCDBYP1
AO
CCD Bypass (Decouple to Analog Ground Through 0.1
µF)
29
PGACONT1
AI
Coarse PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1
µF)
30
PGACONT2
AI
Fine PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1
µF)
31
ACVSS
P
Analog Ground
32
CLAMP_BIAS
AO
Clamp Bias Level (Decouple to Analog Ground Through 0.1
µF)
33
ACVDD
P
+3 V Analog Supply
34
ACVDD
AI
+3 V Analog Supply
35
ACVDD
AI
+3 V Analog Supply
36
INT_BIAS1
AO
Internal Bias Level (Decouple to Analog Ground Through 0.1
µF)
37
CMLEVEL
AO
Common-Mode Level (Decouple to Analog Ground Through 0.1
µF)
38
INT_BIAS2
AO
Internal Bias Level (Decouple to Analog Ground Through 0.1
µF)
39
MODE2
DI
ADC Test Mode Control (See Digital Output Data Control)
40
MODE1
DI
ADC Test Mode Control (See Digital Output Data Control)
41
ADVSS
P
Analog Ground
42
ADVDD
P
+3 V Analog Supply
43
ADVDD
P
+3 V Analog Supply
44
ADVSS
P
Analog Ground
45
ADVSS
P
Analog Ground
46
SUBST
P
Substrate (Connect to Analog Ground)
47
VRB
AO
Bottom Reference Bypass (Decouple to Analog Ground Through 0.1
µF)
48
VRT
AO
Top Reference Bypass (Decouple to Analog Ground Through 0.1
µF)
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
101112
36 35 34 33 32
27 26 25
31 30 29 28
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD9801
VRT
VRB
SUBST
ADVSS
ADVSS
ADVDD
ADVDD
ADVSS
MODE1
MODE2
INT_BIAS2
CMLEVEL
DRVSS
DSUBST
DVSS
ADCCLK
DVDD
STBY
PBLK
CLPOB
SHP
SHD
CLPDM
DVSS


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