AD9051

–10–

REV. A

Overdrive of the Analog Input

Special care was taken in the design of the analog input section

of the AD9051 to prevent damage and corruption of data when

the input is overdriven. The nominal input range is +1.875 V

to 3.125 V (1.25 V p-p centered at 2.5 V). Out-of-range com-

parators detect when the analog input signal is out of this range

and the input buffer is clamped. The digital outputs are locked

at their maximum or minimum value (i.e., all “0” or all “1”).

This precludes the digital outputs changing to an invalid value

when the analog input is out of range.

The input is protected to one volt outside the power supply

rails. For nominal power (+5 V and ground), the analog input

will not be damaged with signals from +5.5 V to –0.5 V.

Timing

The performance of the AD9051 is very insensitive to the duty

cycle of the clock. Pulsewidth variations of as much as

±15%

for encode rates of 40 MSPS and

± 10% for encode rates of

60 MSPS will cause no degradation in performance. (See Fig-

ure 17, SNR vs. Duty Cycle.)

The AD9051 provides latched data outputs, with five pipeline

after the rising edge of the encode command (refer to Fig-

ure 1, Timing Diagram). The length of the output data lines

and loads placed on them should be minimized to reduce tran-

sients within the AD9051; these transients can detract from the

converter’s dynamic performance.

Power Dissipation

The power dissipation specification in the parameter table is

measured under the following conditions: encode is 60 MSPS,

analog input is –FS.

As shown in Figure 3, the actual power dissipation varies based

on these conditions. For instance, reducing the clock rate will

reduce power as expected for CMOS-type devices. The loading

determines the power dissipated in the output stages.

The analog input frequency and amplitude in conjunction with

the clock rate determine the switching rate of the output data

bits. Power dissipation increases as more data bits switch at

faster rates. For instance, if the input is a dc signal that is out of

range, no output bits will switch. This minimizes power in the

output stages, but is not realistic from a usage standpoint.

The dissipation in the output stages can be minimized by inter-

facing the outputs to 3 V logic (refer to Using the AD9051, 3 V

System). The lower output swings minimize power consump-

× V

DD

2

× Update Rate).

Voltage Reference

A stable and accurate +2.5 V voltage reference is built into the

AD9051 (Pin 3, VREFOUT). In normal operation the internal

reference is used by strapping together Pins 3 and 4 of the

AD9051. The internal reference has 500

µA of extra drive cur-

rent that can be used for other circuits.

Some applications may require greater accuracy, improved

temperature performance, or adjustment of the gain of the

AD9051, which cannot be obtained by using the internal refer-

ence. For these applications, an external +2.5 V reference can

be used to connect to Pin 4 of the AD9051. The VREFIN

requires 2

µA of drive current.

The input range can be adjusted by varying the reference volt-

age applied to the AD9051. No appreciable degradation in

performance occurs when the reference is adjusted

±5%. The

full-scale range of the ADC tracks reference voltage changes

linearly.

EVALUATION BOARD

The AD9051 evaluation board is a convenient and easy way to

evaluate the performance of the AD9051.

Analog Input

The evaluation board requires a 1.25 V p-p input. The signal is

buffered by an AD9631 op amp in the unity gain configuration.

The signal is then ac coupled before entering the AD9051

where a dc offset is internally generated. Leave E3 unconnected

to E4 for usage with the AD9631. To evaluate performance

without this buffer, remove the AD9631 and connect E3 to E4.

Keep E1 connected to E2 for use in the low bandwidth mode

(50 MHz). Removing this connector will enable high band-

width mode (130 MHz). Low bandwidth is the recommended

mode of operation in order to minimize any high frequency

noise coupling into the input of the AD9051.

Encode

The evaluation board is driven with a TTL or CMOS clock

into a clock buffer of ac type CMOS logic. This buffer will

drive the encode to the AD9051, the data latches, and a “data

ready.”

Data Out

The digital data is captured by a pair 74ACQ574 latches. Any

unused connector pins should be grounded to the device that is

capturing data from the evaluation board. This minimizes any

grounding loops that may degrade performance. A separate

power plane is provided for supplying the latches, clock buffer,

and digital outputs of the AD9051. This supply can be 3 V or

5V.

Layout

The AD9051 is not layout sensitive if some important guide-

lines are met. The evaluation board layout provides an ex-

ample where these guidelines have been followed to optimize

performance.

• Provide a solid ground plane connecting both analog and

digital sections. Cuts in this plane near the AD9051 should

be kept to a minimum.

• Excellent bypassing is essential. All capacitors should be

placed as close as possible to the AD9051. No vias should

be used to connect capacitors to the AD9051 as this may

create a parasitic inductance that can reduce bypassing

effectiveness.

The AD9051 evaluation board is provided as a design example

for customers of Analog Devices. ADI makes no warranties

express, statutory, or implied regarding merchantability of

fitness for a particular purpose.