AD9050

–8–

REV. B

THEORY OF OPERATION

Refer to the block diagram on the front page.

The AD9050 employs a subranging architecture with digital

error correction. This combination of design techniques en-

sures true 10-bit accuracy at the digital outputs of the converter.

At the input, the analog signal is buffered by a high speed differ-

ential buffer and applied to a track-and-hold (T/H) that holds

the analog value present when the unit is strobed with an

ENCODE command. The conversion process begins on the

rising edge of this pulse. The two stage architecture completes a

coarse and then a fine conversion of the T/H output signal.

Error correction and decode logic correct and align data from

the two conversions and present the result as a 10-bit parallel

digital word. Output data are strobed on the rising edge of the

ENCODE command. The subranging architecture results in

five pipeline delays for the output data. Refer to the AD9050

Timing Diagram.

USING THE AD9050

3 V System

The digital input and outputs of the AD9050 can be easily

configured to directly interface to 3 V logic systems. The en-

code input (Pin 13) is TTL compatible with a logic threshold of

1.5 V. This input is actually a CMOS stage (refer to Equivalent

Encode Input Stage) with a TTL threshold, allowing operation

with TTL, CMOS and 3 V CMOS logic families. Using 3 V

CMOS logic allows the user to drive the encode directly without

the need to translate to +5 V. This saves the user power and

board space. As with all high speed data converters, the clock

signal must be clean and jitter free to prevent the degradation of

dynamic performance.

The AD9050 outputs can also directly interface to 3 V logic

systems. The digital outputs are standard CMOS stages (refer

to AD9050 Output Stage) with isolated supply pins (Pins 20, 22

levels vary respectively. By connecting Pins 20 and 22 to the

3 V logic supply, the AD9050 will supply 3 V output levels.

Care should be taken to filter and isolate the output supply of

the AD9050 as noise could be coupled into the ADC, limiting

performance.

Analog Input

The analog input of the AD9050 is a differential input buffer

(refer to AD9050 Equivalent Analog Input). The differential

inputs are internally biased at +3.3 V, obviating the need for

external biasing. Excellent performance is achieved whether the

analog inputs are driven single-ended or differential (for best

dynamic performance, impedances at AIN and AINB should

match).

Figure 16 shows typical connections for the analog inputs when

using the AD9050 in a dc coupled system with single ended

signals. All components are powered from a single +5 V supply.

The AD820 is used to offset the ground referenced input signal

to the level required by the AD9050.

AC coupling of the analog inputs of the AD9050 is easily ac-

complished. Figure 17 shows capacitive coupling of a single

ended signal while Figure 18 shows transformer coupling differ-

entially into the AD9050.

+5V

AD8041

1k

Ω

1k

Ω

+5V

AD9050

9

10

+5V

1k

–0.5V to +0.5V

1k

Ω

0.1µF

0.1µF

Figure 16. Single Supply, Single Ended, DC Coupled

AD9050

+5V

AD8011

1k

Ω

1k

Ω

+5V

AD9050

9

10

–5V

–0.5V to +0.5V

0.1µF

0.1µF

Figure 17. Single Ended, Capacitively Coupled AD9050

+5V

AD8011

1k

Ω

1k

Ω

+5V

9

10

–5V

–0.5V to +0.5V

0.1µF

AD9050

T1-1T

50

Ω

Figure 18. Differentially Driven AD9050 Using Trans-

former Coupling

The AD830 provides a unique method of providing dc level shift

for the analog input. Using the AD830 allows a great deal of

flexibility for adjusting offset and gain. Figure 19 shows the

AD830 configured to drive the AD9050. The offset is provided

by the internal biasing of the AD9050 differential input (Pin 9).

For more information regarding the AD830, see the AD830

data sheet.

–0.5V to +0.5V

1

2

3

4

AD830

+15V

–5V

710

9

0.1

µF

+5V

AD9050

Figure 19. Level Shifting with the AD830