AD28msp02

REV. 0

–6–

Gain

OG2

OG1

OG0

+6 dB

0

0

0

+3 dB

0

0

1

0 dB

0

1

0

–3 dB

0

1

1

–6 dB

1

0

0

–9 dB

1

0

1

–12 dB

1

1

0

–15 dB

1

1

1

Gain settings are accurate within

±0.6 dB.

(Control Register is set to 0x0000 at RESET. Reserved Bits

10–15 must be set to 0 for all Control Register writes.)

Table II. Control Word Write Format

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

OG2

OG1

OG0

0

PWDD

PWDA ADBY

DABY IMS

IPS

Serial Data Output

The AD28msp02’s SPORT will begin transmitting data to the

host processor at an 8 kHz rate when the PWDD and PWDA

bits (Bits 4, 5) of the control register are set to 1. In the pro-

gram shown in Figure 6, the instructions

AX0 = 0x30; { Write control word to take }

TX0 = AX0; { AD28msp02 out of powerdown }

accomplish this by writing 0x30 to the AD28msp02’s control

register. There is a short start-up time (after the end of this con-

trol register write) before the AD28msp02 raises SDOFS and

begins transmitting data; see Figure 11.

At the 13 MHz MCLK frequency, data is transmitted at an

8 kHz rate with a single 16-bit word transmitted every 125

µs.

While data is being output, the AD28msp02 asserts SDOFS at

an 8 kHz rate. Each 16-bit word transfer begins one serial clock

cycle after SDOFS is asserted.

Serial Data Input

The host processor must initiate data transfers to the

AD28msp02 by asserting the serial data input frame sync

(SDIFS) high. The 16-bit word transfer begins one serial clock

cycle after SDIFS is asserted. The DATA/CNTRL line must be

driven high when SDIFS is driven high.

The host processor must assert SDIFS shortly after the rising

edge of SCLK and must maintain SDIFS high for one cycle.

Data is then driven from the host processor (to the SDI input)

shortly after the rising edge of the next SCLK and is clocked

into the AD28msp02 on the falling edge of SCLK in that cycle.

Each bit of a 16-bit data word is thus clocked into the

AD28msp02 on the falling edge of SCLK (MSB first).

If SDIFS is asserted high again before the end of the present

data word transfer, it is not recognized until the falling edge of

SCLK in the last (LSB) cycle.

(Note: Exact SPORT timing requirements are defined in the

“Specifications” section of this data sheet.)

CONTROL REGISTER

The AD28msp02’s control register configures the device for

various modes of operation including ADC and DAC gain set-

tings, ADC input mux selection, filter bypass, and powerdown.

The AD28msp02’s host processor can read and write to the

control register through the AD28msp02’s serial port (SPORT)

by driving the DATA/CNTRL pin low.

The control register is cleared (set to 0x0000) when the

AD28msp02 is reset.

Control Register Writes

To write the control register, the host processor must assert

DATA/CNTRL low when it asserts SDIFS. If the MSB of

the bit stream is also low, the SPORT recognizes the incoming

serial data as a new control word and copies it to the

AD28msp02’s control register. The format for the control word

write is shown in Table II; reserved Bits 10-15 must be set to

zero.

0

IPS

Analog input preamplifier select: 1 = insert (+20 dB), 0 = bypass (0 dB)

1

IMS

Analog input multiplexer select: 1 = AUX input, 0 = NORM input

2

DABY

DAC high-pass filter bypass select: 0 = insert, 1 = bypass

3

ADBY

ADC high-pass filter bypass select: 0 = insert, 1 = bypass

4

PWDA

Powerdown analog: 0 = powerdown, 1 = operating

5

PWDD

Powerdown digital: 0 = powerdown, 1 = operating

7–9

OG2-OG0

Analog output gain setting (for D/A output PGA)

10–15

Reserved