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AD28MSP01 Datasheet(PDF) 20 Page - Analog Devices |
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AD28MSP01 Datasheet(HTML) 20 Page - Analog Devices |
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20 / 28 page  AD28msp01 REV. A –20– TIMING PARAMETERS Parameter Min Max Unit Clock Signals Timing Requirement: FMCK MCLK Frequency 13.824 13.824 MHz ± 50 ppm tMCK MCLK Period 72.34 72.34 ns tMKL MCLK Width Low 0.5tMCK – 10 0.5tMCK + 10 ns tMKH MCLK Width High 0.5tMCK – 10 0.5tMCK + 10 ns Switching Characteristic: tSCK SCLK Period 8tMCK – 10 8tMCK + 10 ns tSKL SCLK Width Low 4tMCK – 10 4tMCK + 10 ns tSKH SCLK Width High 4tMCK – 10 4tMCK + 10 ns Control Signals Timing Requirement: tRSP RESET Width Low 5tMCK 1 ns NOTE 1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 1000 processor cycles assuming stable CLKIN (not including crystal oscillator start-up time). MCLK SCLK t MCK t MKL t MKH t SKH t SCK t SKL Figure 16. Clock Signals Serial Port 3-State Parameter Min Max Unit Switching Characteristic: tSPD CS Low to SDO, SDOFS, SCLK Disable 20 ns tSPE CS High to SDO, SDOFS, SCLK Enable 0 ns tSPV CS High to SDO, SDOFS, SCLK Valid 25 ns CS t SPD t SPV t SPE SDO SDOFS SCLK Figure 17. Serial Port 3-State |
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