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AD28MSP01 Datasheet(PDF) 19 Page - Analog Devices |
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AD28MSP01 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 28 page  AD28msp01 REV. A –19– DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter Min Typ Max Unit Test Condition VIH Input High Voltage 2.4 V VDD = max VIL Input Low Voltage 0.8 V VDD = min VOH Output High Voltage 2.4 V VDD = min, IOH = –0.5 mA VOL Output Low Voltage 0.4 V VDD = min, IOL = 2 mA IIH High Level Input Current 10 µAV DD = max, VIN = max IIL Low Level Input Current 10 µAV DD = max, VIN = 0 V IOZL Low Level Output 3-State Leakage Current 10 µAV DD = max, VIN = max IOZH High Level Output 3-State Leakage Current 10 µAV DD = max, VIN = 0 V CI Digital Input Capacitance 1 10 pF 1Guaranteed but not tested. ANALOG INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter Min Typ Max Unit ADC: IL Input Leakage Current at VIN 10 nA RI Input Resistance at VIN 100 M Ω CIL Input Load Capacitance at VFB 10 pF VINMAX Maximum Input Range 1 3.156 V p-p DAC: Ro Output Resistance 1 Ω VOFF Output DC Offset 2 –400 400 mV COL Output Load Capacitance 100 pF VO Maximum Voltage Output Swing (p-p) Across RL Single-Ended 3.156 V Differential 6.312 V RL Load Resistance 2 k Ω Test Conditions for all analog interface tests: Unity input gain, no load on analog output (VOUTP–VOUTN). 1At unity gain on input. 2Between V OUTP and VOUTN. POWER DISSIPATION Symbol Parameter Min Typ Max Unit VCC Analog Operating Voltage 4.75 5.0 5.25 V VDD Digital Operating Voltage 4.75 5.0 5.25 V ICC Analog Operating Current Active 1 24 35 mA IDD Digital Operating Current Active1 11 20 mA P1 Power Dissipation Active’ 350 mW ICC Analog Operating Current Inactive 2 300 µA IDD Digital Operating Current Inactive2 200 µA P0 Power Dissipation Inactive 2 4.0 mW Test conditions: VDD = VCC = 5.0 V, MCLK frequency 13.824 MHz, no load on digital pins, analog inputs ac-coupled to ground, no load on analog output (VOUTP–VOUTN). 1Active: AD28msp01 operational (PWDD and PWDA set to 1 in Control Register 1). 2Inactive: AD28msp01 in power-down state (PWDD and PWDA set to 0 in Control Register 1) and MCLK tied to V DD. |
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