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AD28MSP01 Datasheet(PDF) 2 Page - Analog Devices |
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AD28MSP01 Datasheet(HTML) 2 Page - Analog Devices |
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2 / 28 page  AD28msp01 REV. A –2– CS t CONV t BAUD t BIT M CLK RESET ANALOG SIGMA-DELTA MODULATOR DIGITAL DECIMATION FILTER DIGITAL ANTI-ALIASING LOW-PASS FILTER DIGITAL HIGH-PASS FILTER RESAMPLING INTERPOLATION FILTER SERIAL PORT 1 1.728 MHz 16 28.8/32.0/38.4 kHz 16 7.2/8.0/9.6 kHz 16 7.2/8.0/9.6 kHz SDI SDIFS SDO SDOFS SCLK V IN VOLTAGE REFERENCE ANALOG SMOOTHING FILTER DIGITAL SIGMA-DELTA MODULATOR DIGITAL INTERPOLATION FILTER DIGITAL ANTI-IMAGING LOW-PASS FILTER 1 1.728 MHz 16 1.728 MHz 16 28.8/32.0/38.4 kHz 16 7.2/8.0/9.6 kHz V OUT+ V OUT– V FB OUTPUT DIFF. AMP TSYNC r CONV rBAUD r BIT CLOCK GENERATION CONTROL REGISTERS INTERNAL CLOCK CONTROL CIRCUITRY AND SEQUENCER 500k Ω 16-BIT SIGMA-DELTA ADC 16-BIT SIGMA-DELTA DAC INPUT AMP Figure 1. AD28msp01 Block Diagram PIN DESCRIPTIONS Name Type Description Analog Interface VIN I Analog input to the inverting terminal of the input amplifier. VFB O Feedback terminal of the input amplifier. VOUTP O Analog output from the noninverting terminal of the output differential amplifier. VOUTN O Analog output from inverting terminal of the output differential amplifier. Serial Interface SCLK O/Z Serial clock used for clocking data or control bits to/from the serial port (SPORT). The frequency of this clock is 1.7280 MHz. This pin is 3-stated when the CS is low. SDI I Serial data input of the SPORT. Both data and control information are input on this pin. This pin is ignored when CS is low. SDO O/Z Serial data output of the SPORT. Both data and control information are output on this pin. This pin is 3-stated when CS is low. SDIFS I Framing synchronization signal for serial data transfers to the AD28msp01 (via the SDI pin). This pin is ignored when CS is low. Name Type Description SDOFS O/Z Framing synchronization signal for serial data transfers from the AD28msp01 (via the SDO pin). This pin is 3-stated when CS is low. Clock Generation TSYNC I Transmit synchronization clock. This signal is used to synchronize the transmit clocks and the converter clocks to an external terminal/ bit-rate clock. It is used in the V.32 TSYNC and Asynchronous TSYNC modes and is ignored in other operating modes. The frequency of the external clock must be programmed in Control Register 0. This pin must be tied high or low if it is not being used. TBIT O Transmit bit rate clock. This is an output clock whose frequency is programmable via Control Register 3. It is synchronized with the TCONV clock. TBAUD O Transmit baud rate clock. This is an output clock whose frequency is programmable via Control Register 3. It is synchronized with the TCONV clock. |
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Similar Description - AD28MSP01 |
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