AD28msp01

REV. A

–15–

FROM MODEM TX

TO MODEM RX

AD28msp01

A/D

DATA

REGISTER 2

CONTROL

REGISTER 4

RX PHASE ADJUST

ANALOG IN

MCLK

16

16

DSP Processor

D/A

DATA

REGISTER 0

16

ANALOG OUT

TCONV

TBIT

TBAUD

PHASE ADJUST

TX CLOCKS

TX CLOCKS

RCONV

RBIT

RBAUD

PHASE ADJUST

CONVERT

START

RX CLOCKS

FROM MODEM TX

TO MODEM RX

CONVERT

START

CONTROL

REGISTER 5

TX PHASE ADJUST

16

Figure 11. Asynchronous Fallback Mode Block Diagram

Operating Mode Summary

Table III summarizes the operating modes.

Table III. Operating Mode Summary

Internal Filter

Initial Phase

Phase Adjust

Operation

Control

Lock After

Normal DPLL* Register

Resampling

Synchronous To:

Register 0

Mode

Entering Mode

Operation

Programmable†

Interpolator

ADC

DAC

OP 2-0

Async Fallback

no phase lock

no phase lock

RCV, TX

not used

RCONV

TCONV

0 0 0

Async TSYNC

TCONV lock

TCONV lock

RCV

not used

RCONV

TCONV

1 1 1

to TSYNC

to TSYNC

V.32 TSYNC

RCONV lock

TCONV lock

RCV

Input synchronous

TCONV

TCONV

1 0 0

to TCONV

to TSYNC

and in phase with

TCONV, Output

synchronous and in

phase with RCONV

V.32 Internal Sync RCONV lock

no phase lock

RCV, TX

Input synchronous

TCONV

TCONV

1 0 1

to TCONV

and in phase with

TCONV, Output

synchronous and in

phase with RCONV

V.32 Loopback

TCONV lock

no phase lock

RCV††

not used

TCONV

TCONV

1 1 0

to RCONV

NOTES

*DPLL—Digital Phase-Locked loop.

†RCV phase adjusted via Control Register 4, TX phase adjusted via Control Register 5.

††Adjusting RCV phase also adjusts TX phase in this mode.

Note: All receive clocks: RBIT, RBAUD are synchronous to RCONV. All transmit clocks: TBIT, TBAUD are synchronous to TCONV.