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AD28MSP01 Datasheet(PDF) 14 Page - Analog Devices |
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AD28MSP01 Datasheet(HTML) 14 Page - Analog Devices |
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14 / 28 page  AD28msp01 REV. A –14– Asynchronous Fallback TSYNC Mode The Asynchronous Fallback TSYNC Mode is shown in Figure 10. TCONV, TBIT and TBAUD are generated internally but phase locked to the external TSYNC input signal. RCONV, RBIT and RBAUD are generated internally and can be phase adjusted with the Receive Phase Adjust Register (Control Register 4). This mode is entered by setting the Operating Mode field in Control Register 0. The RCONV/TCONV rate can be set to 9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field in Control Register 0. The TBIT and TBAUD clock rates are set by adjusting the appropriate bits in Control Register 3. The RBIT and RBAUD clock rates are set by adjusting the appropri- ate bits in Control Register 2. The bit rates, baud rates and TSYNC rate can be set to any combination of clock rates listed in the control register descriptions. AD28msp01 A/D DATA REGISTER 2 CONTROL REGISTER 4 RX PHASE ADJUST ANALOG IN MCLK 16 16 DSP Processor D/A DATA REGISTER 0 16 ANALOG OUT TCONV TBIT TBAUD PHASE ADJUST TX CLOCKS TX CLOCKS RCONV RBIT RBAUD PHASE ADJUST CONVERT START RX CLOCKS DIGITAL PHASE LOCKED LOOP TSYNC FROM MODEM TX TO MODEM RX 16 Figure 10. Asynchronous Fallback TSYNC Driven Mode Block Diagram Asynchronous Fallback Mode The Asynchronous Fallback Mode is shown in Figure 11. TCONV, TBIT and TBAUD are generated internally and can be phase adjusted with the Transmit Phase Adjust Register (Control Register 5). RCONV, RBIT and RBAUD are gener- ated internally and can also be phase adjusted with the Receive Phase Adjust Register (Control Register 4). The digital phase- locked is not used in this operating mode. This mode is entered by setting the Operating Mode field in Control Register 0. The RCONV/TCONV rate can be set to 9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field in Control Register 0. The TBIT and TBAUD clock rates are set by adjusting the appropriate bits in Control Register 3. The RBIT and RBAUD clock rates are set by adjusting the appropri- ate bits in Control Register 2. The bit and baud rates can be set to any combination of clock rates listed in the control register descriptions. |
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