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AD28MSP01 Datasheet(PDF) 12 Page - Analog Devices |
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AD28MSP01 Datasheet(HTML) 12 Page - Analog Devices |
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12 / 28 page  AD28msp01 REV. A –12– V.32 Internal Sync Mode In V.32 Internal Sync Mode, shown in Figure 8, the AD28msp01’s transmit clocks are generated internally. The receive circuitry operates synchronous to the transmit circuitry, but the data can be resampled at a different phase through the resampling inter- polation filter. TCONV, TBIT and TBAUD are generated internally and can be phase adjusted with the Transmit Phase Adjust Register (Control Register 5). RCONV, RBIT and RBAUD are also gen- erated internally and can be phase adjusted with the Receive Phase Adjust Register (Control Register 4). TCONV initiates a new ADC sample update, loads the ADC register (Data Register 2), and loads the DAC register (Data Register 0) with a new sample. The digital resampling interpolation filter can be used for digital resampling of the received signal. Enable this function by setting Bit 9 in Control Register 0. The phase of the resampled signal is adjusted with the Receive Phase Adjust Register. Samples are loaded into the interpolator at the TCONV rate and are resampled at the RCONV rate. When entering V.32 Internal Sync Mode, RCONV is first locked to TCONV. RCONV is then phase adjusted whenever a new value is written to the Receive Phase Adjust Register (Con- trol Register 4). If this mode is entered from a non-V.32 mode, the device performs a soft reset. The time required to lock TCONV to RCONV is dependent on the phase difference be- tween RCONV and TCONV when entering the mode. This mode is entered by setting the Operating Mode field in Control Register 0. The RCONV/TCONV rate can be set to 9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field in Control Register 0. The TBIT and TBAUD clock rates are set by adjusting the appropriate bits in Control Register 3. The RBIT and RBAUD clock rates are set by adjusting the appropri- ate bits in Control Register 2. The bit and baud rates can be set to any combination of clock rates listed in the control register descriptions. ECHO CANCELLATION TO MODEM RX FROM MODEM TX DATA REGISTER 1 DATA REGISTER 3 PHASE ADJUST INTERPOLATION FILTER AD28msp01 A/D DATA REGISTER 2 CONTROL REGISTER 4 RX PHASE ADJUST RX CLOCKS ANALOG IN TX CLOCKS MCLK TCONV TBIT TBAUD PHASE ADJUST D/A DATA REGISTER 0 16 ANALOG OUT CONVERT START 16 16 16 16 16 16 16 DSP Processor RCONV RBIT RBAUD PHASE ADJUST RX CLOCKS TX CLOCKS CONTROL REGISTER 5 TX PHASE ADJUST Figure 8. V.32 Internal Sync Mode Block Diagram |
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