Preliminary W27E020

Publication Release Date: December 1997

- 3 -

Revision A1

Standby Mode

standby mode, all outputs are in a high impedance state, independent of OE and PGM .

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27E020 provides two control inputs for

multiple memory connections. Two-line control provides for lowest possible memory power

dissipation and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are

and transient current peaks produced by the falling and rising edges of CE. Transient current

magnitudes depend on the device output's capacitive and inductive loading. Two-line control and

proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have

a 0.1

inductance capacitor should be placed as close as possible to the device. Additionally, for every eight

devices, a 4.7

µF electrolytic capacitor should be placed at the array's power supply connection

inductances.

TABLE OF OPERATING MODES

MODE

PINS

CE

OE

PGM

A0

A9

OUTPUTS

Read

X

X

X

Output Disable

X

X

X

High Z

Standby (TTL)

X

X

X

X

High Z

Standby (CMOS)

±0.3V

X

X

X

X

High Z

Program

X

X

Program Verify

X

X

Program Inhibit

X

X

X

X

High Z

Erase

FF (Hex)

Erase Verify

X

X

Erase Inhibit

X

X

X

X

High Z

Product Identifier-

manufacturer

X

DA (Hex)

Product Identifier-device

X

85 (Hex)