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ICX081AK Datasheet(PDF) 6 Page - Sony Corporation |
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ICX081AK Datasheet(HTML) 6 Page - Sony Corporation |
6 / 19 page ![]() – 6 – ICX081AK twh tf tr 90% 10% VHL twl H φ1 two H φ2 VRGL VRGLL VRGLH twl VRGH RG waveform VRGLm tr twh tf VCR Point A (3) Horizontal transfer clock waveform Cross-point voltage for the H φ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks H φ1 and Hφ2 is two. (4) Reset gate clock waveform V φH V φH 2 V φRG VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL) /2 Assuming VRGH is the minimum value during the interval twh, then: V φRG = VRGH – VRGL. Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 90% 100% 10% 0% VSUB tr twh tf φM φM 2 (A bias generated within the CCD) V φSUB |
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