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ICX081AK Datasheet(PDF) 3 Page - Sony Corporation |
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ICX081AK Datasheet(HTML) 3 Page - Sony Corporation |
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3 / 19 page  – 3 – ICX081AK Clock Voltage Conditions Item Readout clock voltage VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 V φV VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL V φH VHL VCR V φRG VRGLH – VRGLL VRGL – VRGLm V φSUB 11.64 –0.05 –0.2 –6.85 5.95 –0.25 –0.25 2.7 –0.05 0.5 2.7 17.3 12.0 0 0 –6.5 6.5 3.3 0 1.65 3.3 18.5 12.36 0.05 0.05 –6.15 6.9 0.1 0.1 0.5 0.5 0.5 0.5 3.6 0.05 3.6 0.4 0.5 19.3 V V V V V V V V V V V V V V V V V V 1 2 2 2 2 2 2 2 2 2 2 3 3 3 4 4 4 5 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 V φV = VVHn – VVLn (n = 1 to 4) High-level coupling High-level coupling Low-level coupling Low-level coupling Cross-point voltage Low-level coupling Low-level coupling Horizontal transfer clock voltage Reset gate clock voltage Substrate clock voltage Vertical transfer clock voltage Symbol Min. Typ. Max. Unit Waveform diagram Remarks Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock VDD VL φSUB φRG 11.64 12.0 ∗1 ∗2 ∗2 12.36 V Symbol Min. Typ. Max. Unit Remarks DC Characteristics Item Supply current IDD 6.0 mA Symbol Min. Typ. Max. Unit Remarks ∗1 V L setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. |
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Similar Description - ICX081AK |
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