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ICX081AK Datasheet(PDF) 2 Page - Sony Corporation |
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ICX081AK Datasheet(HTML) 2 Page - Sony Corporation |
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2 / 19 page  – 2 – ICX081AK Against φSUB Against GND Against VL Between input clock pins Storage temperature Operating temperature Block Diagram and Pin Configuration (Top View) Note) : Photo sensor Ye G Ye Mg Ye G Cy Mg Cy G Cy Mg Ye G Ye Mg Ye G Cy Mg Cy G Cy Mg Horizontal Register Note) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin No. 1 2 3 4 5 6 7 8 V φ4 V φ3 V φ2 V φ1 GND GND GND VOUT Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND GND GND Signal output 9 10 11 12 13 14 15 16 VDD GND φSUB CSUB VL φRG H φ1 H φ2 Supply voltage GND Substrate clock Substrate bias ∗1 Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock Symbol Description Pin Description Absolute Maximum Ratings –40 to +10 –50 to +15 –50 to +0.3 –40 to +0.3 –25 to –0.3 to +18 –10 to +18 –10 to +5 –0.3 to +28 –0.3 to +15 to +15 –5 to +5 –13 to +13 –30 to +80 –10 to +60 V V V V V V V V V V V V V °C °C VDD, VOUT, φRG – φSUB V φ1, Vφ3 – φSUB V φ2, Vφ4, VL – φSUB H φ1, Hφ2, GND – φSUB CSUB – φSUB VDD, VOUT, φRG, CSUB – GND V φ1, Vφ2, Vφ3, Vφ4 – GND H φ1, Hφ2 – GND V φ1, Vφ3 – VL V φ2, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins H φ1 – Hφ2 H φ1, Hφ2 – Vφ4 Item Ratings Unit Remarks ∗2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. ∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. ∗2 Pin No. Symbol Description |
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