MT-074

Note that the SHA switches are connected directly to each of the inputs. Switching transients can

be significant, because there is no isolation buffer. The drive amplifier settling time to the

transients must be fast enough so that the amplifier settles to the required accuracy in less than

one-half the sampling period (this settling time must include the effects of any external series

resistance).

The differential input impedance of this structure is dynamic and changes when the SHA

switches between the sample mode and the hold mode. In addition, the impedance is a function

of the analog input frequency.

In the track mode (shown in the figure), the input signal charges and discharges the hold

and the voltage across the hold capacitors is transferred to the outputs.

It is highly recommended that this type of input be driven differentially for common-mode

rejection of the switching transients. While it is possible to drive them single-ended (with one

input connected to the appropriate common-mode voltage), degradation in SFDR will occur

because the even-order distortion products are no longer rejected.

Figure 2 (A) shows each of the differential inputs of a typical unbuffered CMOS ADC as well as

the sampling clock. The inputs were driven with a 50

Ω source resistance. Note that a transient

occurs on each edge of the sampling clock because of the switching action previously described.

Figure 2(B) shows the differential input signal to the ADC under the same conditions as (A).

Note that most of the transient current glitches are cancelled because they are common-mode

signals. Note that for cancellation to be optimum the two inputs must be driven from a balanced

source impedance (the real and reactive components of the impedance must be matched).

Differential charge transient is symmetrical around mid-scale and

dominated by linear component

Common-mode transients cancel with equal source impedance

Note: Data Taken with 50

Ω Source Resistances

(A) SINGLE ENDED

(B) DIFFERENTIAL

SAMPLING CLOCK

SAMPLING CLOCK

Differential charge transient is symmetrical around mid-scale and

dominated by linear component

Common-mode transients cancel with equal source impedance

Note: Data Taken with 50

Ω Source Resistances

(A) SINGLE ENDED

(B) DIFFERENTIAL

SAMPLING CLOCK

SAMPLING CLOCK

Figure 2: Typical Single-Ended (A) and Differential

(B) Input Transients of CMOS Switched Capacitor ADC

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