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CXD2724AQ-3 Datasheet(PDF) 24 Page - Sony Corporation |
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CXD2724AQ-3 Datasheet(HTML) 24 Page - Sony Corporation |
24 / 65 page ![]() – 24 – CXD2724AQ-3 SQC15 SQC14 SQC13 SQC12, SQC11 SQC10 SQC09, SQC08 SQC07, SQC06 SQC05, SQC04 SQC03 to SQC00 LRCK format 0: normal 1: IIS LRCK polarity selection 0: Lch "H" 1: Lch "L" BCK polarity selection 0: Falling edge relative to LRCK edge 1: Rising edge Serial audio SQC12 SQC11 interface setting 0 0 : MSB first/Frontward truncation/24 bits 0 1 : MSB first/Rearward truncation/16 bits 1 0 : MSB first/Rearward truncation/18 bits 1 1 : MSB first/Rearward truncation/20 bits DAC forced mute 0: ON 1: OFF Reserve bit Be sure to set both bits Low when changing the setup register Field C settings. Decimation ratio setting SQC07 SQC06 (SFC mode only) 0 0 : 1/1 (No decimation) Be sure to also set 0 1 : 1/2 decimation SQA11 and SQA10. 1 ∗ : 1/3 decimation BFOT output clock SQC05 SQC04 frequency division 0 0 : 384Fs ratio setting 0 1 : 256Fs 1 0 : 512Fs 1 1 : 768Fs Reserve bit Be sure to set all of these bits Low when changing the setup register Field C settings. normal Lch "H" Falling edge MSB first/Frontward truncation/24 bits ON all "L" 1/1 (No decimation) 384Fs all "L" (3) Field C Table 6-3. Setup Register Field C Data section bit Control contents When reset Note) BCK polarity selection (SQC13) is valid only in slave mode. Fix to "0" in master mode. |
Similar Part No. - CXD2724AQ-3 |
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Similar Description - CXD2724AQ-3 |
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