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CXD2724AQ-3 Datasheet(PDF) 21 Page - Sony Corporation |
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CXD2724AQ-3 Datasheet(HTML) 21 Page - Sony Corporation |
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21 / 65 page  – 21 – CXD2724AQ-3 Data section write begins after XLAT rises, and here also transfer must be performed with LSB first, with tDS and tDH restrictions. In addition, after XLAT rises at the starting point for sending the data section, wait for 3t + 20ns or more for the first SCK rise (tLSD). When 16 bits of this write is repeated, REDY goes Low within 4t + 50ns, and the microcomputer is informed of waiting status for the SV cycle, which is the dedicated data rewrite cycle, by the microcomputer interface (tSBD). When REDY goes High again, the corresponding data is written. The next communication can be restarted by using the REDY signal as follows. • When REDY = Low, the SCK for the next transfer can rise (tBSP ≥ 20ns). • In the same way, when REDY = Low, the XLAT for the next transfer can fall (tLDR ≥ 20ns). REDY will fall due to this communication, but it is prohibited for XLAT to rise for the next transfer before REDY rises. Make sure that the next XLAT rises after REDY rises (tRLP ≥ 20ns). In order to restart the next transfer without using the REDY signal, the following conditions must be observed: • There should be 2t + 40ns or more left between the SCK rise for the final data section and the SCK rise for the next transfer (tSS). • In the same way, the XLAT for the next transfer can fall after waiting for 3t + 20ns or more after the final data section SCK rise (tSLD). The tSS and tSLD here are shorter times than tSBD ≤ 4t + 50ns, so these are rather loose restrictions. However, even in this case the XLAT rise for the next transfer must come after REDY rises (tRLP ≥ 20ns). Further, the restriction for the XLAT fall at the starting point of this transfer from tSLD can be: tSLD ≥ 3t + 20ns |
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