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CXD2724AQ-3 Datasheet(PDF) 20 Page - Sony Corporation |
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CXD2724AQ-3 Datasheet(HTML) 20 Page - Sony Corporation |
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20 / 65 page  – 20 – CXD2724AQ-3 (4)-2. Signal Timing First, address section data and mode section data are sent from the microcomputer, synchronized to SCK, to the RVDT pin. The address section data is 8 bits for both the coefficient RAM and setup register, and the setup register has a length of one word, so optional data can be transferred. Address section data is sent with LSB first. Mode section data is fixed at 8 bits regardless of the transfer contents. The phase relationship between SCK and RV data (data applied to the RVDT pin) has the following restrictions: • RV data must be established before SCK rises (tDS ≥ 20ns). • RV data must be held for 1t + 20ns or more after SCK rises (tDH). SCK itself has the following restrictions: • SCK Low level must be 1t + 20ns or more (tSWL). • SCK High level must be 1t + 20ns or more (tSWH). After the SCK rise which corresponds to the mode section final data, XLAT rises (tSLP ≥ 20ns). The XLAT Low level width must be maintained at 1t + 20ns or more (tLWL). The fall timing is restricted in that even if REDY falls due to SCK during the preceding transfer, 3t + 20ns or more (tSLD) is required from the SCK rise which corresponds to the data section final data. Further, if preceding transfers have been performed and REDY = Low, XLAT must rise after REDY = High. A0 A7 M0 M7 SQ00 SQ15 RVDT SCK XLAT REDY A0 M7 tDH tDS tSWH tSWL tSLD or tLWH tLWL tRLP tLDR tLSD tSLP tBSP tSLP tLDR tRLP tSS tSLD tSBD D0/SQ00 D15/SQ15 Fig. 5-3. Write Timing ∗ t is the cycle of 2/3 the clock frequency applied to the XTLI pin. (512fs) |
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Similar Description - CXD2724AQ-3 |
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