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CXD2724AQ-3 Datasheet(PDF) 17 Page - Sony Corporation |
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CXD2724AQ-3 Datasheet(HTML) 17 Page - Sony Corporation |
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17 / 65 page  – 17 – CXD2724AQ-3 5. Microcomputer Interface [Relevant pins] RVDT, SCK, XLAT, REDY The CXD2724AQ-3 performs the serial audio interface format setting and the coefficient settings such as volume and filter by serial data from the microcomputer. (1) Pin Configuration The four external pins indicated in the table below are assigned to the microcomputer interface. Serial data input from microcomputer. Shift clock for serial data. Input data from RVDT is taken according to the SCK rise. Interprets the 8 bits of RVDT before this signal rises as transfer mode data, and the bits before that as address data. Transfer prohibited while at Low level. Transfer enabled at High. This pin is an open drain, and must be pulled up externally. Symbol RVDT SCK XLAT REDY I/O Function I I I O Table 5-1. Microcomputer Interface External Pins (2) Description of Communication Formats The internal data transfer timing from the microcomputer interface to the coefficient RAM and setup register is called the SV cycle, and is generated once per 1 LRCK. The SV cycle is generated immediately preceding the signal processing program, so it has absolutely no effect on signal processing, and there is no risk of the sound being cut. Address section + Mode section + Data section act as one package of data to transfer data from the microcomputer to the CXD2724AQ-3. [Write] ∗ For coefficient RAM A0 A7 M0 M7 D0 D15 Address section (8 bits) Mode section (8 bits) RVDT SCK XLAT REDY Data section (16 bits) Fig. 5-1. Example of Communication |
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